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Merge pull request #5392 from rocallahan/opt-merge-cleanup

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Some small readability improvements to `OptMergeWorker`
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Emil J 2025-09-25 12:15:33 +02:00 • committed by GitHub
commit 8c8d18f2d8
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2 changed files with 12 additions and 11 deletions
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6
kernel/rtlil.h
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@ -1244,7 +1244,8 @@ private:
public: public:
SigSpec() : width_(0), hash_(0) {} SigSpec() : width_(0), hash_(0) {}
SigSpec(std::initializer_list<RTLIL::SigSpec> parts); SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
SigSpec(const SigSpec &) = default;
SigSpec(SigSpec &&) = default;
SigSpec(const RTLIL::Const &value); SigSpec(const RTLIL::Const &value);
SigSpec(RTLIL::Const &&value); SigSpec(RTLIL::Const &&value);
SigSpec(const RTLIL::SigChunk &chunk); SigSpec(const RTLIL::SigChunk &chunk);
@ -1261,6 +1262,9 @@ public:
SigSpec(const std::set<RTLIL::SigBit> &bits); SigSpec(const std::set<RTLIL::SigBit> &bits);
explicit SigSpec(bool bit); explicit SigSpec(bool bit);
SigSpec &operator=(const SigSpec &rhs) = default;
SigSpec &operator=(SigSpec &&rhs) = default;
inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; } inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; } inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }

17
passes/opt/opt_merge.cc
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@ -25,6 +25,7 @@
#include "libs/sha1/sha1.h" #include "libs/sha1/sha1.h"
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
#include <algorithm>
#include <set> #include <set>
#include <unordered_map> #include <unordered_map>
#include <array> #include <array>
@ -170,24 +171,20 @@ struct OptMergeWorker
} }
} }
if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) || if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) { ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
if (conn1.at(ID::A) < conn1.at(ID::B)) { if (conn1.at(ID::A) < conn1.at(ID::B)) {
RTLIL::SigSpec tmp = conn1[ID::A]; std::swap(conn1[ID::A], conn1[ID::B]);
conn1[ID::A] = conn1[ID::B];
conn1[ID::B] = tmp;
} }
if (conn2.at(ID::A) < conn2.at(ID::B)) { if (conn2.at(ID::A) < conn2.at(ID::B)) {
RTLIL::SigSpec tmp = conn2[ID::A]; std::swap(conn2[ID::A], conn2[ID::B]);
conn2[ID::A] = conn2[ID::B];
conn2[ID::B] = tmp;
} }
} else } else
if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) { if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
conn1[ID::A].sort(); conn1[ID::A].sort();
conn2[ID::A].sort(); conn2[ID::A].sort();
} else } else
if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) { if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
conn1[ID::A].sort_and_unify(); conn1[ID::A].sort_and_unify();
conn2[ID::A].sort_and_unify(); conn2[ID::A].sort_and_unify();
} else } else