diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index 14eec206b..7b5c1df18 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -1090,7 +1090,7 @@ static bool ignored_cell(const RTLIL::IdString& type)
 void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
 {
 	bool is_input_port = false;
-	if (module->sig_norm_index != nullptr && !ignored_cell(type)) {
+	if (module && module->sig_norm_index != nullptr && !ignored_cell(type)) {
 		module->sig_norm_index->sigmap.apply(signal);
 		auto dir = port_dir(portname);
 
@@ -1113,6 +1113,9 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
 	if (!r.second && conn_it->second == signal)
 		return;
 
+	if (!module)
+		return;
+
 	for (auto mon : module->monitors)
 		mon->notify_connect(this, conn_it->first, conn_it->second, signal);
 
diff --git a/kernel/unstable/patch.cc b/kernel/unstable/patch.cc
index 2438229f0..01286c1d3 100644
--- a/kernel/unstable/patch.cc
+++ b/kernel/unstable/patch.cc
@@ -37,6 +37,7 @@ Wire* Patch::addWire(IdString name, int width) {
 
 // TODO code golf
 
+
 RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
 {
 	RTLIL::Wire *wire = addWire(std::move(name));
@@ -76,6 +77,7 @@ void Patch::patch(Cell* old_cell, Cell* new_cell) {
 			if (raw == new_cell)
 				if (dir == PD_OUTPUT || dir == PD_INOUT) {
 					// RAUW
+					// TODO optimized implementation for signorm fanout transfer?
 					old_cell->setPort(port_name, mod->addWire(NEW_ID, sig.size()));
 					new_cell->setPort(port_name, sig);
 					auto* wire = sig.as_wire();
diff --git a/passes/cmds/test_patch.cc b/passes/cmds/test_patch.cc
index 3081034fc..727099a15 100644
--- a/passes/cmds/test_patch.cc
+++ b/passes/cmds/test_patch.cc
@@ -17,17 +17,24 @@ struct TestPatchPass : public Pass {
 		for (auto module : design->selected_modules()) {
 			for (auto cell : module->selected_cells()) {
 				if (cell->type == ID($add)) {
+					Cell* add = cell;
+					log_assert(add->getPort(ID::B).is_wire());
+					log_assert(add->getPort(ID::B).known_driver());
+					auto neg = add->getPort(ID::B).as_wire()->driverCell();
+					log_assert(neg->type == ID($not));
+
+
 					RTLIL::Patch patcher;
 					patcher.mod = module;
 					patcher.map = SigMap(module);
-					RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub));
-					// sub->connections_ = cell->connections();
-					sub->parameters = cell->parameters;
-					sub->connections_[ID::A] = cell->getPort(ID::A);
-					sub->connections_[ID::B] = cell->getPort(ID::B);
-					sub->connections_[ID::Y] = cell->getPort(ID::Y);
-					log_cell(sub);
-					patcher.patch(cell, sub);
+					auto new_cell = patcher.addNeg(NEW_ID, patcher.Sub(NEW_ID, neg->getPort(ID::A), cell->getPort(ID::A)), SigSpec());
+					// // sub->connections_ = cell->connections();
+					// sub->parameters = add->parameters;
+					// sub->connections_[ID::A] = add->getPort(ID::A);
+					// sub->connections_[ID::B] = add->getPort(ID::B);
+					// sub->connections_[ID::Y] = add->getPort(ID::Y);
+					log_cell(new_cell);
+					patcher.patch(add, new_cell);
 				}
 			}
 		}