From 2468b391bfb146005569941835079e496fd32c3b Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 24 Jan 2026 01:48:15 +0000 Subject: [PATCH 1/2] Make `compare_signals` produce a total order. Currently when `s1` and `s2` are different bits of the same wire, it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to return false. This means the calling code will call `assign_map.add()` for both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2` should be consistently preferred. So fix that by preferring the `SigBit` with the smaller bit offset. --- passes/opt/opt_clean.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3892c7581..661871d87 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -271,6 +271,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo return conns.check_any(s2); } + if (w1 == w2) + return s2.offset < s1.offset; + if (w1->port_output != w2->port_output) return w2->port_output; From 7d53d64a47b13e26105348961876c179a285a201 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 24 Jan 2026 01:51:34 +0000 Subject: [PATCH 2/2] Make the call to `compare_signals()` easier to read. The negation here is confusing. The intent of the code is "if `s1` is preferred over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit` in `assign_map`", so write the code that way instead of "if `s2` is not preferred over `s1` ...". This doesn't change any behavior now that `compare_signals()` is a total order, i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal. Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's already a noop in that case. --- passes/opt/opt_clean.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 661871d87..ccdcbf7f9 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -346,7 +346,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1); - if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) + if (compare_signals(s2, s1, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } }