From 8bbc3c359cb28024a10c4ecaa1767057bcbaed82 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 May 2026 15:16:09 +0200 Subject: [PATCH] Remove id2cstr uses in our code base --- backends/cxxrtl/cxxrtl_backend.cc | 2 +- .../source/code_examples/stubnets/stubnets.cc | 6 ++-- frontends/verific/verific.cc | 4 +-- kernel/rtlil.cc | 6 ++-- passes/cmds/scc.cc | 6 ++-- passes/cmds/select.cc | 18 ++++++------ passes/cmds/test_select.cc | 4 +-- passes/equiv/equiv_make.cc | 4 +-- passes/fsm/fsm_detect.cc | 2 +- passes/hierarchy/hierarchy.cc | 28 +++++++++---------- passes/sat/cutpoint.cc | 4 +-- passes/sat/expose.cc | 18 ++++++------ passes/sat/freduce.cc | 10 +++---- passes/sat/miter.cc | 2 +- passes/techmap/iopadmap.cc | 14 +++++----- techlibs/ice40/ice40_braminit.cc | 2 +- 16 files changed, 64 insertions(+), 66 deletions(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 3ebe62b90..ac69bda27 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -3420,7 +3420,7 @@ struct CxxrtlWorker { if (!design->selected_whole_module(module)) if (design->selected_module(module)) - log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name)); + log_cmd_error("Can't handle partially selected module `%s'!\n", module); if (!design->selected_module(module)) continue; diff --git a/docs/source/code_examples/stubnets/stubnets.cc b/docs/source/code_examples/stubnets/stubnets.cc index 566d24b18..41fb66e82 100644 --- a/docs/source/code_examples/stubnets/stubnets.cc +++ b/docs/source/code_examples/stubnets/stubnets.cc @@ -27,7 +27,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // count output lines for this module (needed only for summary output at the end) int line_count = 0; - log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name)); + log("Looking for stub wires in module %s:\n", module); // For all ports on all cells for (auto &cell_iter : module->cells_) @@ -74,11 +74,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // report stub bits and/or stub wires, don't report single bits // if called with report_bits set to false. if (GetSize(stub_bits) == GetSize(sig)) { - log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name)); + log(" found stub wire: %s\n", wire); } else { if (!report_bits) continue; - log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name)); + log(" found wire with stub bits: %s [", wire); for (int bit : stub_bits) log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit); log("]\n"); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ec3d21ccd..6b876c0f1 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1492,10 +1492,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma design->add(module); if (is_blackbox(nl)) { - log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); + log("Importing blackbox module %s.\n", module); module->set_bool_attribute(ID::blackbox); } else { - log("Importing module %s.\n", RTLIL::id2cstr(module->name)); + log("Importing module %s.\n", module); } import_attributes(module->attributes, nl, nl); if (module->name.isPublic()) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 020a4ec0c..31efff63d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1579,7 +1579,7 @@ void RTLIL::Module::makeblackbox() void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict &) { - log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name)); + log_error("Class doesn't support expand_interfaces (module: `%s')!\n", name.unescape()); } bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *) @@ -1591,7 +1591,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dictname)); + log(" %s", c); cell2scc[c] = sccList.size(); scc.insert(c); } @@ -201,7 +201,7 @@ struct SccWorker if (!nofeedbackMode && cellToNextCell[cell].count(cell)) { log("Found an SCC:"); pool scc; - log(" %s", RTLIL::id2cstr(cell->name)); + log(" %s", cell); cell2scc[cell] = sccList.size(); scc.insert(cell); sccList.push_back(scc); @@ -221,7 +221,7 @@ struct SccWorker run(cell, 0, maxDepth); } - log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name)); + log("Found %d SCCs in module %s.\n", int(sccList.size()), module); } void select(RTLIL::Selection &sel) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index bcb34d1d4..1fcc35dfa 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -25,8 +25,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -using RTLIL::id2cstr; - static std::vector work_stack; static bool match_ids(RTLIL::IdString id, const std::string &pattern) @@ -1022,9 +1020,9 @@ static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::S for (auto mod : design->all_selected_modules()) { if (whole_modules && sel->selected_whole_module(mod->name)) - desc += stringf("%s\n", id2cstr(mod->name)); + desc += stringf("%s\n", mod); for (auto it : mod->selected_members()) - desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name)); + desc += stringf("%s/%s\n", mod, it); } if (push_selection) design->pop_selection(); return desc; @@ -1414,7 +1412,7 @@ struct SelectPass : public Pass { if (arg == "-module" && argidx+1 < args.size()) { RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); if (design->module(mod_name) == nullptr) - log_cmd_error("No such module: %s\n", id2cstr(mod_name)); + log_cmd_error("No such module: %s\n", mod_name.unescape()); design->selected_active_module = mod_name.str(); got_module = true; continue; @@ -1527,10 +1525,10 @@ struct SelectPass : public Pass { for (auto mod : design->all_selected_modules()) { if (sel->selected_whole_module(mod->name) && list_mode) - log("%s\n", id2cstr(mod->name)); + log("%s\n", mod); if (!list_mod_mode) for (auto it : mod->selected_members()) - LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name)) + LOG_OBJECT("%s/%s\n", mod->name.unescape().c_str(), it->name.unescape().c_str()) } if (count_mode) { @@ -1654,10 +1652,10 @@ struct SelectPass : public Pass { if (sel.full_selection) log("*\n"); for (auto &it : sel.selected_modules) - log("%s\n", id2cstr(it)); + log("%s\n", it.unescape()); for (auto &it : sel.selected_members) for (auto &it2 : it.second) - log("%s/%s\n", id2cstr(it.first), id2cstr(it2)); + log("%s/%s\n", it.first.unescape(), it2.unescape()); return; } @@ -1779,7 +1777,7 @@ static void log_matches(const char *title, Module *module, const T &list) log("\n%d %s:\n", int(matches.size()), title); std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str()); for (auto id : matches) - log(" %s\n", RTLIL::id2cstr(id)); + log(" %s\n", id.unescape()); } } diff --git a/passes/cmds/test_select.cc b/passes/cmds/test_select.cc index 0076500ce..4a3bbc539 100644 --- a/passes/cmds/test_select.cc +++ b/passes/cmds/test_select.cc @@ -144,10 +144,10 @@ struct TestSelectPass : public Pass { for (auto *mod : sub_sel) { if (mod->is_selected_whole()) { - log_debug(" Adding %s.\n", id2cstr(mod->name)); + log_debug(" Adding %s.\n", mod); selected_modules.insert(mod->name); } else for (auto *memb : mod->selected_members()) { - log_debug(" Adding %s.%s.\n", id2cstr(mod->name), id2cstr(memb->name)); + log_debug(" Adding %s.%s.\n", mod, memb); selected_members[mod->name].insert(memb); } } diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 3aa3fac63..602ad776d 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -285,11 +285,11 @@ struct EquivMakeWorker for (int i = 0; i < wire->width; i++) { if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); + log(" Skipping signal bit %s [%d]: undriven on gold side.\n", gold_wire, i); continue; } if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); + log(" Skipping signal bit %s [%d]: undriven on gate side.\n", gate_wire, i); continue; } equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index dfe99f512..7f5107ce9 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -61,7 +61,7 @@ ret_false: if (recursion_monitor.count(cellport.first)) { log_warning("logic loop in mux tree at signal %s in module %s.\n", - log_signal(sig), RTLIL::id2cstr(module->name)); + log_signal(sig), module); goto ret_false; } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 67475eda0..f41c19672 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -87,7 +87,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, if (decl.index > 0) { portwidths[decl.portname] = max(portwidths[decl.portname], 1); portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]); - log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname)); + log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::unescape_id(decl.portname)); if (indices.count(decl.index) > ports.size()) log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size())); if (indices.count(decl.index) == 0) @@ -108,10 +108,10 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, indices.erase(d.index); ports[d.index-1] = d; portwidths[d.portname] = max(portwidths[d.portname], 1); - log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname)); + log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::unescape_id(d.portname)); goto found_matching_decl; } - log_error("Can't match port %s.\n", RTLIL::id2cstr(portname)); + log_error("Can't match port %s.\n", portname.unescape()); found_matching_decl:; portnames.erase(portname); } @@ -133,9 +133,9 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, mod->fixup_ports(); for (auto ¶ : parameters) - log(" ignoring parameter %s.\n", RTLIL::id2cstr(para)); + log(" ignoring parameter %s.\n", para.unescape()); - log(" module %s created.\n", RTLIL::id2cstr(mod->name)); + log(" module %s created.\n", mod); } } @@ -597,7 +597,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check int idx = it.second.first, num = it.second.second; if (design->module(cell->type) == nullptr) - log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + log_error("Array cell `%s.%s' of unknown type `%s'.\n", module, cell, cell->type.unescape()); RTLIL::Module *mod = design->module(cell->type); @@ -613,12 +613,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } } if (mod->wire(portname) == nullptr) - log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", module, cell, conn.first.unescape()); int port_size = mod->wire(portname)->width; if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) - log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); + log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", module, cell, conn.first.unescape()); conn.second = conn.second.extract(port_size*idx, port_size); } } @@ -1219,7 +1219,7 @@ struct HierarchyPass : public Pass { if (read_id_num(p.first, &id)) { if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) { log(" Failed to map positional parameter %d of cell %s.%s (%s).\n", - id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + id, mod, cell, cell->type.unescape()); } else { params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1])); } @@ -1241,7 +1241,7 @@ struct HierarchyPass : public Pass { RTLIL::Module *module = work.first; RTLIL::Cell *cell = work.second; log("Mapping positional arguments of cell %s.%s (%s).\n", - RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + module, cell, cell->type.unescape()); dict new_connections; for (auto &conn : cell->connections()) { int id; @@ -1249,7 +1249,7 @@ struct HierarchyPass : public Pass { std::pair key(design->module(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", - id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + id, module, cell, cell->type.unescape()); new_connections[conn.first] = conn.second; } else new_connections[pos_map.at(key)] = conn.second; @@ -1283,7 +1283,7 @@ struct HierarchyPass : public Pass { if (m == nullptr) log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n", - RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + module, cell, cell->type.unescape()); // Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) { @@ -1312,11 +1312,11 @@ struct HierarchyPass : public Pass { if (parent_wire == nullptr) log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n", - RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + wire, module, cell, cell->type.unescape()); if (parent_wire->width != wire->width) log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n", parent_wire->width, wire->width, - RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); + wire, module, cell, cell->type.unescape()); cell->setPort(wire->name, parent_wire); } cell->attributes.erase(ID::wildcard_port_conns); diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index ff1ae2628..6c4023a6a 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -132,7 +132,7 @@ struct CutpointPass : public Pass { if (cell->input(conn.first)) for (auto bit : sigmap(conn.second)) if (wire_drivers.count(bit)) { - log_debug(" Treating inout port '%s' as input.\n", id2cstr(conn.first)); + log_debug(" Treating inout port '%s' as input.\n", conn.first.unescape()); do_cut = false; break; } @@ -140,7 +140,7 @@ struct CutpointPass : public Pass { if (do_cut) { module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); if (cell->input(conn.first)) { - log_debug(" Treating inout port '%s' as output.\n", id2cstr(conn.first)); + log_debug(" Treating inout port '%s' as output.\n", conn.first.unescape()); for (auto bit : sigmap(conn.second)) wire_drivers.insert(bit); } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index ef00a6956..b5f2a437c 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -471,7 +471,7 @@ struct ExposePass : public Pass { { if (!w->port_input) { w->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s\n", module, w); wire_map[w] = NEW_ID; } } @@ -479,7 +479,7 @@ struct ExposePass : public Pass { { if (!w->port_output) { w->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s\n", module, w); } if (flag_cut) { @@ -555,7 +555,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); wire_q->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name)); + log("New module port: %s/%s\n", module, wire_q); RTLIL::SigSig connect_q; for (size_t i = 0; i < wire_bits_vec.size(); i++) { @@ -569,12 +569,12 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width); wire_d->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); + log("New module port: %s/%s\n", module, wire_d); module->connect(RTLIL::SigSig(wire_d, info.sig_d)); RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c"); wire_c->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); + log("New module port: %s/%s\n", module, wire_c); if (info.clk_polarity) { module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); } else { @@ -590,7 +590,7 @@ struct ExposePass : public Pass { { RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r"); wire_r->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); + log("New module port: %s/%s\n", module, wire_r); if (info.arst_polarity) { module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); } else { @@ -604,7 +604,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); wire_v->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); + log("New module port: %s/%s\n", module, wire_v); module->connect(RTLIL::SigSig(wire_v, info.arst_value)); } } @@ -638,7 +638,7 @@ struct ExposePass : public Pass { if (p->port_output) w->port_input = true; - log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); + log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape()); RTLIL::SigSpec sig; if (cell->hasPort(p->name)) @@ -660,7 +660,7 @@ struct ExposePass : public Pass { if (ct.cell_output(cell->type, it.first)) w->port_input = true; - log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); + log("New module port: %s/%s (%s)\n", module, w, cell->type.unescape()); if (w->port_input) module->connect(RTLIL::SigSig(it.second, w)); diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 4b0669c25..d2ca52b6f 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -139,7 +139,7 @@ struct FindReducedInputs if (ez_cells.count(drv.first) == 0) { satgen.setContext(&sigmap, "A"); if (!satgen.importCell(drv.first)) - log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); + log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape()); satgen.setContext(&sigmap, "B"); if (!satgen.importCell(drv.first)) log_abort(); @@ -256,7 +256,7 @@ struct PerformReduction std::pair> &drv = drivers.at(out); if (celldone.count(drv.first) == 0) { if (!satgen.importCell(drv.first)) - log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); + log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, drv.first->type.unescape()); celldone.insert(drv.first); } int max_child_depth = 0; @@ -595,14 +595,14 @@ struct FreduceWorker void dump() { - std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter); + std::string filename = stringf("%s_%s_%05d.il", dump_prefix, module, reduce_counter); log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename); Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); } int run() { - log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name)); + log("Running functional reduction on module %s:\n", module); CellTypes ct; ct.setup_internals(); @@ -749,7 +749,7 @@ struct FreduceWorker } } - log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name)); + log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, module); return rewired_sigbits; } }; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 55a41909d..9df88b304 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -128,7 +128,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name); } - log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); + log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape()); RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index d7667d6f5..0a12d4881 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -389,7 +389,7 @@ struct IopadmapPass : public Pass { if (wire->port_input && !wire->port_output) { if (inpad_celltype.empty()) { - log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map input port %s.%s: Missing option -inpad.\n", module, wire); continue; } celltype = inpad_celltype; @@ -398,7 +398,7 @@ struct IopadmapPass : public Pass { } else if (!wire->port_input && wire->port_output) { if (outpad_celltype.empty()) { - log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map output port %s.%s: Missing option -outpad.\n", module, wire); continue; } celltype = outpad_celltype; @@ -407,7 +407,7 @@ struct IopadmapPass : public Pass { } else if (wire->port_input && wire->port_output) { if (inoutpad_celltype.empty()) { - log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map inout port %s.%s: Missing option -inoutpad.\n", module, wire); continue; } celltype = inoutpad_celltype; @@ -417,11 +417,11 @@ struct IopadmapPass : public Pass { log_abort(); if (!flag_bits && wire->width != 1 && widthparam.empty()) { - log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); + log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", module, wire); continue; } - log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype); + log("Mapping port %s.%s using %s.\n", module, wire, celltype); if (flag_bits) { @@ -442,7 +442,7 @@ struct IopadmapPass : public Pass { if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) - cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); + cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", wire, i)); cell->attributes[ID::keep] = RTLIL::Const(1); } } @@ -465,7 +465,7 @@ struct IopadmapPass : public Pass { if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) - cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); + cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(wire->name.unescape()); cell->attributes[ID::keep] = RTLIL::Const(1); } diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 0d07e2522..4a1849642 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -46,7 +46,7 @@ static void run_ice40_braminit(Module *module) continue; /* Open file */ - log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file); + log("Processing %s : %s\n", cell, init_file); std::ifstream f; f.open(init_file.c_str());