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pmgen: hold sigmap pointer instead of owning it

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This commit is contained in:
Emil J. Tywoniak 2026-04-14 18:05:33 +02:00
parent 647541a4c1
commit 8bbb0acdda
10 changed files with 61 additions and 42 deletions
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24
techlibs/xilinx/xilinx_dsp.cc
View file

@ -64,7 +64,7 @@ static Cell* addDsp(Module *module) {
return cell;
}
void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &selected_cells)
{
std::deque<Cell*> simd12_add, simd12_sub;
std::deque<Cell*> simd24_add, simd24_sub;
@ -73,9 +73,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
if (!cell->type.in(ID($add), ID($sub)))
continue;
SigSpec Y = cell->getPort(ID::Y);
if (!Y.is_chunk())
if (!Y.is_chunk() || Y.is_wire())
continue;
if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
Wire* wire = (*sigmap)(Y).as_wire();
if (!wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
continue;
if (GetSize(Y) > 25)
continue;
@ -366,7 +367,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
@ -553,7 +554,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
@ -676,7 +677,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) {
SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstport != IdString()) {
@ -795,19 +796,20 @@ struct XilinxDspPass : public Pass {
if (design->scratchpad_get_bool("xilinx_dsp.multonly"))
continue;
SigMap sigmap(module);
// Experimental feature: pack $add/$sub cells with
// (* use_dsp48="simd" *) into DSP48E1's using its
// SIMD feature
if (family == "xc7")
xilinx_simd_pack(module, module->selected_cells());
xilinx_simd_pack(module, &sigmap, module->selected_cells());
// Match for all features ([ABDMP][12]?REG, pre-adder,
// post-adder, pattern detector, etc.) except for CREG
if (family == "xc7") {
xilinx_dsp_pm pm(module, module->selected_cells());
xilinx_dsp_pm pm(module, &sigmap, module->selected_cells());
pm.run_xilinx_dsp_pack(xilinx_dsp_pack);
} else if (family == "xc6s" || family == "xc3sda") {
xilinx_dsp48a_pm pm(module, module->selected_cells());
xilinx_dsp48a_pm pm(module, &sigmap, module->selected_cells());
pm.run_xilinx_dsp48a_pack(xilinx_dsp48a_pack);
}
// Separating out CREG packing is necessary since there
@ -819,14 +821,14 @@ struct XilinxDspPass : public Pass {
// PREG of an upstream DSP that had not been visited
// yet
{
xilinx_dsp_CREG_pm pm(module, module->selected_cells());
xilinx_dsp_CREG_pm pm(module, &sigmap, module->selected_cells());
pm.run_xilinx_dsp_packC(xilinx_dsp_packC);
}
// Lastly, identify and utilise PCOUT -> PCIN,
// ACOUT -> ACIN, and BCOUT-> BCIN dedicated cascade
// chains
{
xilinx_dsp_cascade_pm pm(module, module->selected_cells());
xilinx_dsp_cascade_pm pm(module, &sigmap, module->selected_cells());
pm.run_xilinx_dsp_cascade();
}
}

3
techlibs/xilinx/xilinx_srl.cc
View file

@ -244,7 +244,8 @@ struct XilinxSrlPass : public Pass {
log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
for (auto module : design->selected_modules()) {
auto pm = xilinx_srl_pm(module, module->selected_cells());
SigMap sigmap(module);
auto pm = xilinx_srl_pm(module, &sigmap, module->selected_cells());
pm.ud_fixed.minlen = minlen;
pm.ud_variable.minlen = minlen;