diff --git a/passes/opt/peepopt.cc b/passes/opt/peepopt.cc index fa7cf74a0..0a067968d 100644 --- a/passes/opt/peepopt.cc +++ b/passes/opt/peepopt.cc @@ -101,11 +101,12 @@ struct PeepoptPass : public Pass { { did_something = true; + SigMap sigmap(module); while (did_something) { did_something = false; - peepopt_pm pm(module); + peepopt_pm pm(module, &sigmap); pm.setup(module->selected_cells()); diff --git a/passes/pmgen/generate.h b/passes/pmgen/generate.h index 85e208774..959c0f981 100644 --- a/passes/pmgen/generate.h +++ b/passes/pmgen/generate.h @@ -85,7 +85,8 @@ void generate_pattern(std::function)> run, const if (timeout++ > 10000) log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n"); - pm matcher(mod, mod->cells()); + SigMap sigmap(mod); + pm matcher(mod, &sigmap, mod->cells()); matcher.rng(1); matcher.rngseed += modcnt; diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index d2adbbdd9..38772964d 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -361,7 +361,7 @@ with open(outfile, "w") as f: print("struct {}_pm {{".format(prefix), file=f) print(" Module *module;", file=f) - print(" SigMap sigmap;", file=f) + print(" SigMap *sigmap;", file=f) print(" std::function on_accept;", file=f) print(" bool setup_done;", file=f) print(" bool generate_mode;", file=f) @@ -423,7 +423,7 @@ with open(outfile, "w") as f: print("", file=f) print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f) - print(" for (auto bit : sigmap(sig)) {", file=f) + print(" for (auto bit : (*sigmap)(sig)) {", file=f) print(" if (bit.wire == nullptr) continue;", file=f) print(" sigusers[bit].insert(cell);", file=f) print(" }", file=f) @@ -453,12 +453,12 @@ with open(outfile, "w") as f: print(" SigSpec port(Cell *cell, IdString portname) {", file=f) print(" try {", file=f) - print(" return sigmap(cell->getPort(portname));", file=f) + print(" return (*sigmap)(cell->getPort(portname));", file=f) print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f) print(" }", file=f) print("", file=f) print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f) - print(" return sigmap(cell->connections_.at(portname, defval));", file=f) + print(" return (*sigmap)(cell->connections_.at(portname, defval));", file=f) print(" }", file=f) print("", file=f) @@ -475,21 +475,21 @@ with open(outfile, "w") as f: print(" int nusers(const SigSpec &sig) {", file=f) print(" pool users;", file=f) - print(" for (auto bit : sigmap(sig))", file=f) + print(" for (auto bit : (*sigmap)(sig))", file=f) print(" for (auto user : sigusers[bit])", file=f) print(" users.insert(user);", file=f) print(" return GetSize(users);", file=f) print(" }", file=f) print("", file=f) - print(" {}_pm(Module *module, const vector &cells) :".format(prefix), file=f) - print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) + print(" {}_pm(Module *module, SigMap *map, const vector &cells) :".format(prefix), file=f) + print(" module(module), sigmap(map), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) print(" setup(cells);", file=f) print(" }", file=f) print("", file=f) - print(" {}_pm(Module *module) :".format(prefix), file=f) - print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) + print(" {}_pm(Module *module, SigMap *map) :".format(prefix), file=f) + print(" module(module), sigmap(map), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) print(" }", file=f) print("", file=f) diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index f6d6a3f93..ec6cb2929 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -163,8 +163,10 @@ struct TestPmgenPass : public Pass { } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) - while (test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_chain)) {} + for (auto module : design->selected_modules()) { + SigMap sigmap(module); + while (test_pmgen_pm(module, &sigmap, module->selected_cells()).run_reduce(reduce_chain)) {} + } } void execute_reduce_tree(std::vector args, RTLIL::Design *design) @@ -182,8 +184,10 @@ struct TestPmgenPass : public Pass { } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) - test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree); + for (auto module : design->selected_modules()) { + SigMap sigmap(module); + test_pmgen_pm(module, &sigmap, module->selected_cells()).run_reduce(reduce_tree); + } } void execute_eqpmux(std::vector args, RTLIL::Design *design) @@ -201,8 +205,10 @@ struct TestPmgenPass : public Pass { } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) - test_pmgen_pm(module, module->selected_cells()).run_eqpmux(opt_eqpmux); + for (auto module : design->selected_modules()) { + SigMap sigmap(module); + test_pmgen_pm(module, &sigmap, module->selected_cells()).run_eqpmux(opt_eqpmux); + } } void execute_generate(std::vector args, RTLIL::Design *design) diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc index 6c3b365b0..8c145f6f0 100644 --- a/techlibs/ice40/ice40_dsp.cc +++ b/techlibs/ice40/ice40_dsp.cc @@ -314,8 +314,10 @@ struct Ice40DspPass : public Pass { // TODO Disabled signorm because swap_names breaks fanout logic design->sigNormalize(false); - for (auto module : design->selected_modules()) - ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp); + for (auto module : design->selected_modules()) { + SigMap sigmap(module); + ice40_dsp_pm(module, &sigmap, module->selected_cells()).run_ice40_dsp(create_ice40_dsp); + } } } Ice40DspPass; diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc index 9f0648b38..aa1c43283 100644 --- a/techlibs/ice40/ice40_wrapcarry.cc +++ b/techlibs/ice40/ice40_wrapcarry.cc @@ -48,7 +48,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) cell->setPort(ID(I0), st.lut->getPort(ID(I0))); auto I3 = st.lut->getPort(ID(I3)); - if (pm.sigmap(CI) == pm.sigmap(I3)) { + if ((*pm.sigmap)(CI) == (*pm.sigmap)(I3)) { cell->setParam(ID(I3_IS_CI), State::S1); I3 = State::Sx; } @@ -112,9 +112,10 @@ struct Ice40WrapCarryPass : public Pass { design->sigNormalize(false); for (auto module : design->selected_modules()) { - if (!unwrap) - ice40_wrapcarry_pm(module, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry); - else { + if (!unwrap) { + SigMap sigmap(module); + ice40_wrapcarry_pm(module, &sigmap, module->selected_cells()).run_ice40_wrapcarry(create_ice40_wrapcarry); + } else { for (auto cell : module->selected_cells()) { if (cell->type != ID($__ICE40_CARRY_WRAPPER)) continue; diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc index df7093bc5..98016814c 100644 --- a/techlibs/microchip/microchip_dsp.cc +++ b/techlibs/microchip/microchip_dsp.cc @@ -89,7 +89,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) { // input/output ports SigSpec D = ff->getPort(ID::D); - SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); + SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); @@ -206,7 +206,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) { // input/output ports SigSpec D = ff->getPort(ID::D); - SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); + SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { @@ -318,8 +318,11 @@ struct MicrochipDspPass : public Pass { } extra_args(args, argidx, design); + // TODO deduplicate all this noise with xilinx_dsp.cc + for (auto module : design->selected_modules()) { + SigMap sigmap(module); if (design->scratchpad_get_bool("microchip_dsp.multonly")) continue; @@ -333,7 +336,7 @@ struct MicrochipDspPass : public Pass { // check for an accumulator pattern based on whether // a post-adder and PREG are both present AND // if PREG feeds into this post-adder. - microchip_dsp_pm pm(module, module->selected_cells()); + microchip_dsp_pm pm(module, &sigmap, module->selected_cells()); pm.run_microchip_dsp_pack(microchip_dsp_pack); } @@ -346,13 +349,13 @@ struct MicrochipDspPass : public Pass { // PREG of an upstream DSP that had not been visited // yet { - microchip_dsp_CREG_pm pm(module, module->selected_cells()); + microchip_dsp_CREG_pm pm(module, &sigmap, module->selected_cells()); pm.run_microchip_dsp_packC(microchip_dsp_packC); } // Lastly, identify and utilise PCOUT -> PCIN chains { - microchip_dsp_cascade_pm pm(module, module->selected_cells()); + microchip_dsp_cascade_pm pm(module, &sigmap, module->selected_cells()); pm.run_microchip_dsp_cascade(); } } diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index f0669da6c..f6acb68d3 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -205,8 +205,10 @@ struct QlDspMacc : public Pass { } extra_args(a_Args, argidx, a_Design); - for (auto module : a_Design->selected_modules()) - ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); + for (auto module : a_Design->selected_modules()) { + SigMap sigmap(module); + ql_dsp_macc_pm(module, &sigmap, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); + } } } QlDspMacc; diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index 22e6bce5b..61794f539 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -64,7 +64,7 @@ static Cell* addDsp(Module *module) { return cell; } -void xilinx_simd_pack(Module *module, const std::vector &selected_cells) +void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector &selected_cells) { std::deque simd12_add, simd12_sub; std::deque simd24_add, simd24_sub; @@ -73,9 +73,10 @@ void xilinx_simd_pack(Module *module, const std::vector &selected_cells) if (!cell->type.in(ID($add), ID($sub))) continue; SigSpec Y = cell->getPort(ID::Y); - if (!Y.is_chunk()) + if (!Y.is_chunk() || Y.is_wire()) continue; - if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd")) + Wire* wire = (*sigmap)(Y).as_wire(); + if (!wire->get_strpool_attribute(ID(use_dsp)).count("simd")) continue; if (GetSize(Y) > 25) continue; @@ -366,7 +367,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) { SigSpec D = ff->getPort(ID::D); - SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); + SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { @@ -553,7 +554,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) { SigSpec D = ff->getPort(ID::D); - SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); + SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { @@ -676,7 +677,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport) { SigSpec D = ff->getPort(ID::D); - SigSpec Q = pm.sigmap(ff->getPort(ID::Q)); + SigSpec Q = (*pm.sigmap)(ff->getPort(ID::Q)); if (!A.empty()) A.replace(Q, D); if (rstport != IdString()) { @@ -795,19 +796,20 @@ struct XilinxDspPass : public Pass { if (design->scratchpad_get_bool("xilinx_dsp.multonly")) continue; + SigMap sigmap(module); // Experimental feature: pack $add/$sub cells with // (* use_dsp48="simd" *) into DSP48E1's using its // SIMD feature if (family == "xc7") - xilinx_simd_pack(module, module->selected_cells()); + xilinx_simd_pack(module, &sigmap, module->selected_cells()); // Match for all features ([ABDMP][12]?REG, pre-adder, // post-adder, pattern detector, etc.) except for CREG if (family == "xc7") { - xilinx_dsp_pm pm(module, module->selected_cells()); + xilinx_dsp_pm pm(module, &sigmap, module->selected_cells()); pm.run_xilinx_dsp_pack(xilinx_dsp_pack); } else if (family == "xc6s" || family == "xc3sda") { - xilinx_dsp48a_pm pm(module, module->selected_cells()); + xilinx_dsp48a_pm pm(module, &sigmap, module->selected_cells()); pm.run_xilinx_dsp48a_pack(xilinx_dsp48a_pack); } // Separating out CREG packing is necessary since there @@ -819,14 +821,14 @@ struct XilinxDspPass : public Pass { // PREG of an upstream DSP that had not been visited // yet { - xilinx_dsp_CREG_pm pm(module, module->selected_cells()); + xilinx_dsp_CREG_pm pm(module, &sigmap, module->selected_cells()); pm.run_xilinx_dsp_packC(xilinx_dsp_packC); } // Lastly, identify and utilise PCOUT -> PCIN, // ACOUT -> ACIN, and BCOUT-> BCIN dedicated cascade // chains { - xilinx_dsp_cascade_pm pm(module, module->selected_cells()); + xilinx_dsp_cascade_pm pm(module, &sigmap, module->selected_cells()); pm.run_xilinx_dsp_cascade(); } } diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc index 04c657df6..fa0a3906a 100644 --- a/techlibs/xilinx/xilinx_srl.cc +++ b/techlibs/xilinx/xilinx_srl.cc @@ -244,7 +244,8 @@ struct XilinxSrlPass : public Pass { log_cmd_error("'-fixed' and/or '-variable' must be specified.\n"); for (auto module : design->selected_modules()) { - auto pm = xilinx_srl_pm(module, module->selected_cells()); + SigMap sigmap(module); + auto pm = xilinx_srl_pm(module, &sigmap, module->selected_cells()); pm.ud_fixed.minlen = minlen; pm.ud_variable.minlen = minlen;