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https://github.com/YosysHQ/yosys
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Refactor MREG and PREG to out_dffe subpattern
This commit is contained in:
Eddie Hung
parent
e64e650f9c
commit
8b8a68b38a
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@ -7,12 +7,12 @@ state <IdString> postAddAB postAddMuxAB
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state <bool> ffAenpol ffADenpol ffBenpol ffCenpol ffDenpol ffMenpol ffPenpol
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state <bool> ffAenpol ffADenpol ffBenpol ffCenpol ffDenpol ffMenpol ffPenpol
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state <int> ffPoffset
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state <int> ffPoffset
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMmux ffP ffPmux
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// subpattern
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// subpattern
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state <SigSpec> argQ
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state <SigSpec> argQ argD
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state <bool> ffenpol
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state <bool> ffenpol
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udata <SigSpec> dffD
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <SigBit> dffclock
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udata <Cell*> dff dffmux
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udata <Cell*> dff dffmux
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udata <bool> dffenpol
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udata <bool> dffenpol
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@ -159,76 +159,20 @@ code argQ ffD ffDmux ffDenpol sigD clock
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}
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}
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endcode
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endcode
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match ffMmux
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code argD ffM ffMmux ffMenpol sigM sigP clock
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if param(dsp, \MREG).as_int() == 0
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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if dsp->parameters.at(\USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY"
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argD = sigM;
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if nusers(sigM) == 2
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subpattern(out_dffe);
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select ffMmux->type.in($mux)
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if (dff) {
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choice <IdString> BA {\B, \A}
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ffM = dff;
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// new-value net must have exactly two users: dsp and ffMmux
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clock = dffclock;
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select nusers(port(ffMmux, BA)) == 2
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if (dffmux) {
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define <IdString> AB (BA == \B ? \A : \B)
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ffMmux = dffmux;
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// keep-last-value net must have at least three users: ffMmux, ffM, downstream sink(s)
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ffMenpol = dffenpol;
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select nusers(port(ffMmux, AB)) >= 3
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}
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// ffMmux output must have two users: ffMmux and ffM.D
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sigM = dffQ;
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select nusers(port(ffMmux, \Y)) == 2
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}
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filter GetSize(unextend(port(ffMmux, BA))) <= GetSize(sigM)
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filter unextend(port(ffMmux, BA)) == sigM.extract(0, GetSize(unextend(port(ffMmux, BA))))
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// Remaining bits on sigM must not have any other users
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filter nusers(sigM.extract_end(GetSize(unextend(port(ffMmux, BA))))) <= 1
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define <bool> pol (AB == \A)
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set ffMenpol pol
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optional
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endmatch
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code sigM
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if (ffMmux)
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sigM = port(ffMmux, \Y);
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endcode
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match ffM_enable
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if ffMmux
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if nusers(sigM) == 2
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select ffM_enable->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffM_enable, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ffM_enable, \D) === sigM
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index <SigSpec> port(ffM_enable, \Q) === port(ffMmux, ffMenpol ? \A : \B)
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endmatch
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match ffM
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if dsp->parameters.at(\USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY"
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if !ffM_enable
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if param(dsp, \MREG).as_int() == 0
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if nusers(sigM) == 2
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select ffM->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffM, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ffM, \D) === sigM
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optional
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endmatch
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code ffM clock sigM sigP
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if (ffM_enable) {
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log_assert(!ffM);
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ffM = ffM_enable;
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}
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}
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if (ffM) {
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sigM = port(ffM, \Q);
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for (auto b : sigM)
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffM, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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// No enable mux possible without flop
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else if (ffMmux)
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reject;
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sigP = sigM;
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sigP = sigM;
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endcode
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endcode
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@ -268,90 +212,25 @@ code sigC sigP
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}
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}
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endcode
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endcode
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match ffPmux
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code argD ffP ffPmux ffPenpol sigP clock
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if param(dsp, \PREG).as_int() == 0
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if (param(dsp, \PREG).as_int() == 0) {
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPmux
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPmux
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if !ffMmux || postAdd || nusers(sigP) == 3
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if ((ffMmux && !postAdd && nusers(sigP) == 3) ||
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// Otherwise new-value net must have exactly two users: dsp and ffPmux
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// Otherwise new-value net must have exactly two users: dsp and ffPmux
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if (ffMmux && !postAdd) || nusers(sigP) == 2
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((!ffMmux || postAdd) && nusers(sigP) == 2)) {
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argD = sigP;
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select ffPmux->type.in($mux)
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subpattern(out_dffe);
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// ffPmux output must have two users: ffPmux and ffP.D
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if (dff) {
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select nusers(port(ffPmux, \Y)) == 2
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ffP = dff;
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filter GetSize(port(ffPmux, \Y)) >= GetSize(sigP)
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clock = dffclock;
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if (dffmux) {
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slice offset GetSize(port(ffPmux, \Y))
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ffPmux = dffmux;
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filter offset+GetSize(sigP) <= GetSize(port(ffPmux, \Y))
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ffPenpol = dffenpol;
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choice <IdString> BA {\B, \A}
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}
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filter port(ffPmux, BA).extract(offset, GetSize(sigP)) == sigP
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sigP = dffQ;
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}
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define <IdString> AB (BA == \B ? \A : \B)
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}
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// keep-last-value net must have at least three users: ffPmux, ffP, downstream sink(s)
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filter nusers(port(ffPmux, AB)) >= 3
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define <bool> pol (AB == \A)
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set ffPenpol pol
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set ffPoffset offset
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optional
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endmatch
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code sigP
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if (ffPmux)
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sigP.replace(port(ffPmux, ffPenpol ? \B : \A), port(ffPmux, \Y));
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endcode
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match ffP_enable
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if ffPmux
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if nusers(sigP) == 2
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select ffP_enable->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffP_enable, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ffP_enable, \D) === port(ffPmux, \Y)
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index <SigSpec> port(ffP_enable, \Q) === port(ffPmux, ffPenpol ? \A : \B)
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filter GetSize(port(ffP_enable, \D)) >= GetSize(sigP)
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filter ffPoffset+GetSize(sigP) <= GetSize(port(ffP_enable, \D))
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filter port(ffP_enable, \D).extract(ffPoffset, GetSize(sigP)) == sigP
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endmatch
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match ffP
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if !ffP_enable
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if param(dsp, \PREG).as_int() == 0
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// If ffMmux and no postAdd new-value net must have exactly three users: ffMmux, ffM and ffPmux
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if !ffMmux || postAdd || nusers(sigP) == 3
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// Otherwise new-value net must have exactly two users: dsp and ffPmux
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if (ffMmux && !postAdd) || nusers(sigP) == 2
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select ffP->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffP, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffP, \D)) >= GetSize(sigP)
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slice offset GetSize(port(ffP, \D))
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filter offset+GetSize(sigP) <= GetSize(port(ffP, \D))
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filter port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
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optional
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endmatch
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code ffP sigP clock
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if (ffP_enable) {
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log_assert(!ffP);
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ffP = ffP_enable;
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}
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}
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if (ffP) {
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for (auto b : port(ffP, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffP, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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sigP.replace(port(ffP, \D), port(ffP, \Q));
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}
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// No enable mux possible without flop
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else if (ffPmux)
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reject;
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endcode
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endcode
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match postAddMux
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match postAddMux
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@ -391,6 +270,8 @@ code
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accept;
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accept;
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endcode
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endcode
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// #######################
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subpattern in_dffe
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subpattern in_dffe
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arg argQ clock ffenpol
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arg argQ clock ffenpol
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@ -457,3 +338,89 @@ code
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else
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else
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dffmux = nullptr;
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dffmux = nullptr;
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endcode
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endcode
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// #######################
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subpattern out_dffe
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arg argD clock ffenpol
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arg unextend
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match ffmux
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select ffmux->type.in($mux)
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// ffmux output must have two users: ffmux and ff.D
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select nusers(port(ffmux, \Y)) == 2
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filter GetSize(port(ffmux, \Y)) >= GetSize(argD)
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choice <IdString> BA {\B, \A}
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// new-value net must have exactly two users: (upstream) and ffmux
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select nusers(port(ffmux, BA)) == 2
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slice offset GetSize(port(ffmux, \Y))
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filter offset+GetSize(argD) <= GetSize(port(ffmux, \Y))
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filter port(ffmux, BA).extract(offset, GetSize(argD)) == argD
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define <IdString> AB (BA == \B ? \A : \B)
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// keep-last-value net must have at least three users: ffmux, ff, downstream sink(s)
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select nusers(port(ffmux, AB)) >= 3
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filter GetSize(unextend(port(ffmux, BA))) <= GetSize(argD)
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filter unextend(port(ffmux, BA)) == argD.extract(0, GetSize(unextend(port(ffmux, BA))))
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// Remaining bits on argD must not have any other users
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filter nusers(argD.extract_end(GetSize(unextend(port(ffmux, BA))))) <= 1
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define <bool> pol (AB == \A)
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set ffenpol pol
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semioptional
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endmatch
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code argD
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if (ffmux) {
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dffmux = ffmux;
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dffenpol = ffenpol;
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argD = port(ffmux, \Y);
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}
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else
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dffmux = nullptr;
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endcode
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match ff_enable
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if ffmux
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select ff_enable->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff_enable, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff_enable, \D) === argD
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index <SigSpec> port(ff_enable, \Q) === port(ffmux, ffenpol ? \A : \B)
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endmatch
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match ff
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if !ff_enable
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff, \D) === argD
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semioptional
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endmatch
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code
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if (ff_enable)
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dff = ff_enable;
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else
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dff = ff;
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log_dump("ffM", dff, dffmux);
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if (dff) {
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dffQ = port(dff, \Q);
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for (auto b : dffQ)
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if (b.wire->get_bool_attribute(\keep))
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reject;
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if (clock != SigBit()) {
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if (port(dff, \CLK) != clock)
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reject;
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}
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dffclock = port(dff, \CLK);
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}
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// No enable mux possible without flop
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else if (ffmux)
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reject;
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endcode
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