From 8b1f5fba62e2d065d8bc31990927931fb67a4a94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 12 Jan 2023 17:24:31 +0100 Subject: [PATCH] passes: show: Simplify wire bit range logic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin PoviĊĦer --- passes/cmds/show.cc | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index c1a0c35ee..5739c79cd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -261,18 +261,20 @@ struct ShowWorker for (int rep, i = int(sig.chunks().size())-1; i >= 0; i -= rep) { const RTLIL::SigChunk &c = sig.chunks().at(i); int cl, cr; - if (c.wire) { + + cl = c.offset + c.width - 1; + cr = c.offset; + + if (c.is_wire()) { if (c.wire->upto) { - cr = c.wire->start_offset + (c.wire->width - c.offset - 1); + cr = (c.wire->width - 1) - c.offset; cl = cr - (c.width - 1); - } else { - cr = c.wire->start_offset + c.offset; - cl = cr + c.width - 1; } - } else { - cl = c.offset + c.width - 1; - cr = c.offset; + + cl += c.wire->start_offset; + cr += c.wire->start_offset; } + if (!driver && c.wire == nullptr) { RTLIL::State s1 = c.data.front(); for (auto s2 : c.data)