diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f18784b5e..17fe2ec99 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2020,7 +2020,7 @@ specify
 	$setuphold(negedge CLK, negedge SR, 113:125:140, 0:0:0);
 endspecify
 `endif
-`ifdef ICE40_LX
+`ifdef ICE40_LP
 specify
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L79
 	(CIN => COUT) = (118:153:186, 98:128:155);
@@ -2045,7 +2045,7 @@ specify
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L89
 	(I3 => LO) = (249:323:393, 255:332:403);
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
-	(posedge CLK => O) = (504:655:796, 504:655:796);
+	(posedge CLK => (O : 1'bx)) = (504:655:796, 504:655:796);
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91-L92
 	(SR => O) = (559:726:883, 559:726:883);
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
@@ -2109,7 +2109,7 @@ specify
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L101
 	(I3 => LO) = (216:378:583, 226:395:609);
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
-	(posedge CLK => O) = (516:903:1391, 516:903:1391);
+	(posedge CLK => (O : 1'bx)) = (516:903:1391, 516:903:1391);
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103-104
 	(SR => O) = (420:734:1131, 590:1032:1589);
 	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
@@ -2366,7 +2366,7 @@ module SB_SPRAM256KA (
 `endif
 `ifdef ICE40_U
 	specify
-		https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13169-L13182
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13169-L13182
 		$setup(posedge ADDRESS, posedge CLOCK, 268);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13183
 		$setup(CHIPSELECT, posedge CLOCK, 404);
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 5292d1615..170078a7f 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -2,12 +2,23 @@
 
 set -e
 
+declare -A defines=( ["ice40"]="ICE40_HX ICE40_LP ICE40_U" )
+
 echo "Running syntax check on arch sim models"
 for arch in ../../techlibs/*; do
 	find $arch -name cells_sim.v | while read path; do
-		echo -n "Test $path ->"
-		iverilog -t null -I$arch $path
-		echo " ok"
+		arch_name=$(basename -- $arch)
+		if [ "${defines[$arch_name]}" ]; then
+			for def in ${defines[$arch_name]}; do
+				echo -n "Test $path -D$def ->"
+				iverilog -t null -I$arch -D$def $path
+				echo " ok"
+			done
+		else
+			echo -n "Test $path ->"
+			iverilog -t null -I$arch $path
+			echo " ok"
+		fi
 	done
 done