From 8af9979aab5f1434ee7d0e56a85324d78e2fd9f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Mar 2019 09:01:48 -0700
Subject: [PATCH] Revert "Add shregmap -init_msb_first and use in synth_xilinx"
This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.
---
passes/techmap/shregmap.cc | 16 ++--------------
techlibs/xilinx/synth_xilinx.cc | 5 ++---
2 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 6cd9082dc..f20863ba0 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -34,7 +34,7 @@ struct ShregmapOptions
{
int minlen, maxlen;
int keep_before, keep_after;
- bool zinit, init, params, ffe, init_msb_first;
+ bool zinit, init, params, ffe;
dict<IdString, pair<IdString, IdString>> ffcells;
ShregmapTech *tech;
@@ -48,7 +48,6 @@ struct ShregmapOptions
init = false;
params = false;
ffe = false;
- init_msb_first = false;
tech = nullptr;
}
};
@@ -308,8 +307,6 @@ struct ShregmapWorker
initval.push_back(State::S0);
remove_init.insert(bit);
}
- if (opts.init_msb_first)
- std::reverse(initval.begin(), initval.end());
first_cell->setParam("\\INIT", initval);
}
@@ -445,13 +442,9 @@ struct ShregmapPass : public Pass {
log("\n");
log(" -init\n");
log(" map initialized registers to the shift reg, add an INIT parameter to\n");
- log(" generated cells with the initialization value. (First bit to shift out\n");
+ log(" generated cells with the initialization value. (first bit to shift out\n");
log(" in LSB position)\n");
log("\n");
- log(" -init_msb_first\n");
- log(" same as -init, but INIT parameter to have first bit to shift out\n");
- log(" in MSB position.\n");
- log("\n");
log(" -tech greenpak4\n");
log(" map to greenpak4 shift registers.\n");
log("\n");
@@ -522,11 +515,6 @@ struct ShregmapPass : public Pass {
opts.init = true;
continue;
}
- if (args[argidx] == "-init_msb_first") {
- opts.init = true;
- opts.init_msb_first = true;
- continue;
- }
if (args[argidx] == "-params") {
opts.params = true;
continue;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 169f3b7ce..1978ccf21 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -111,7 +111,7 @@ struct SynthXilinxPass : public Pass
log(" dff2dffe\n");
log(" opt -full\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
- log(" shregmap -init_msb_first -params -enpol any_or_none\n");
+ log(" shregmap -init -params -enpol any_or_none\n");
log(" techmap -map +/xilinx/ff_map.v\n");
log(" opt -fast\n");
log("\n");
@@ -262,9 +262,8 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
}
- Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none");
+ Pass::call(design, "shregmap -initt -params -enpol any_or_none");
Pass::call(design, "techmap -map +/xilinx/ff_map.v");
- Pass::call(design, "hierarchy -check");
Pass::call(design, "opt -fast");
}