From 8ae1d758e2771efdc74febd3d2eb33f6cd92e9e0 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 25 Mar 2026 11:50:17 +0100
Subject: [PATCH] opt_expr: with -keepdc disable equality optimization rules
 that break when ports are sigmapped

---
 passes/opt/opt_expr.cc | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 28746ae93..af4d7b436 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1206,8 +1206,13 @@ skip_fine_alu:
 					replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
 					goto next_cell;
 				}
-				if (a[i] == b[i])
-					continue;
+				if (keepdc) {
+					if (!a[i].is_wire() && !b[i].is_wire() && a[i].data != RTLIL::State::Sx && b[i].data != RTLIL::State::Sx && a[i] == b[i])
+						continue;
+				} else {
+					if (a[i] == b[i])
+						continue;
+				}
 				new_a.append(a[i]);
 				new_b.append(b[i]);
 			}