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Move (most of) ExOth and ExAdv slides

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manual/PRESENTATION_ExAdv.tex
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@ -15,790 +15,6 @@ This section contains 4 subsections:
\end{itemize}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Using selections}
\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}
\subsubsection{Simple selections}
\begin{frame}[fragile]{\subsubsecname}
Most Yosys commands make use of the ``selection framework'' of Yosys. It can be used
to apply commands only to part of the design. For example:
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
delete # will delete the whole design, but
delete foobar # will only delete the module foobar.
\end{lstlisting}
\bigskip
The {\tt select} command can be used to create a selection for subsequent
commands. For example:
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select foobar # select the module foobar
delete # delete selected objects
select -clear # reset selection (select whole design)
\end{lstlisting}
\end{frame}
\subsubsection{Selection by object name}
\begin{frame}[fragile]{\subsubsecname}
The easiest way to select objects is by object name. This is usually only done
in synthesis scripts that are hand-tailored for a specific design.
\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select foobar # select module foobar
select foo* # select all modules whose names start with foo
select foo*/bar* # select all objects matching bar* from modules matching foo*
select */clk # select objects named clk from all modules
\end{lstlisting}
\end{frame}
\subsubsection{Module and design context}
\begin{frame}[fragile]{\subsubsecname}
Commands can be executed in {\it module\/} or {\it design\/} context. Until now all
commands have been executed in design context. The {\tt cd} command can be used
to switch to module context.
\bigskip
In module context all commands only effect the active module. Objects in the module
are selected without the {\tt <module\_name>/} prefix. For example:
\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
cd foo # switch to module foo
delete bar # delete object foo/bar
cd mycpu # switch to module mycpu
dump reg_* # print details on all objects whose names start with reg_
cd .. # switch back to design
\end{lstlisting}
\bigskip
Note: Most synthesis scripts never switch to module context. But it is a very powerful
tool for interactive design investigation.
\end{frame}
\subsubsection{Selecting by object property or type}
\begin{frame}[fragile]{\subsubsecname}
Special patterns can be used to select by object property or type. For example:
\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select w:reg_* # select all wires whose names start with reg_
select a:foobar # select all objects with the attribute foobar set
select a:foobar=42 # select all objects with the attribute foobar set to 42
select A:blabla # select all modules with the attribute blabla set
select foo/t:$add # select all $add cells from the module foo
\end{lstlisting}
\bigskip
A complete list of this pattern expressions can be found in the command
reference to the {\tt select} command.
\end{frame}
\subsubsection{Combining selection}
\begin{frame}[fragile]{\subsubsecname}
When more than one selection expression is used in one statement, then they are
pushed on a stack. The final elements on the stack are combined into a union:
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select t:$dff r:WIDTH>1 # all cells of type $dff and/or with a parameter WIDTH > 1
\end{lstlisting}
\bigskip
Special \%-commands can be used to combine the elements on the stack:
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select t:$dff r:WIDTH>1 %i # all cells of type $dff *AND* with a parameter WIDTH > 1
\end{lstlisting}
\medskip
\begin{block}{Examples for {\tt \%}-codes (see {\tt help select} for full list)}
{\tt \%u} \dotfill union of top two elements on stack -- pop 2, push 1 \\
{\tt \%d} \dotfill difference of top two elements on stack -- pop 2, push 1 \\
{\tt \%i} \dotfill intersection of top two elements on stack -- pop 2, push 1 \\
{\tt \%n} \dotfill inverse of top element on stack -- pop 1, push 1 \\
\end{block}
\end{frame}
\subsubsection{Expanding selections}
\begin{frame}[fragile]{\subsubsecname}
Selections of cells and wires can be expanded along connections using {\tt \%}-codes
for selecting input cones ({\tt \%ci}), output cones ({\tt \%co}), or both ({\tt \%x}).
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
# select all wires that are inputs to $add cells
select t:$add %ci w:* %i
\end{lstlisting}
\bigskip
Additional constraints such as port names can be specified.
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
# select all wires that connect a "Q" output with a "D" input
select c:* %co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i
# select the multiplexer tree that drives the signal 'state'
select state %ci*:+$mux,$pmux[A,B,Y]
\end{lstlisting}
\bigskip
See {\tt help select} for full documentation of this expressions.
\end{frame}
\subsubsection{Incremental selection}
\begin{frame}[fragile]{\subsubsecname}
Sometimes a selection can most easily be described by a series of add/delete operations.
The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
from the current selection instead of overwriting it.
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select -none # start with an empty selection
select -add reg_* # select a bunch of objects
select -del reg_42 # but not this one
select -add state %ci # and add mor stuff
\end{lstlisting}
\bigskip
Within a select expression the token {\tt \%} can be used to push the previous selection
on the stack.
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select t:$add t:$sub # select all $add and $sub cells
select % %ci % %d # select only the input wires to those cells
\end{lstlisting}
\end{frame}
\subsubsection{Creating selection variables}
\begin{frame}[fragile]{\subsubsecname}
Selections can be stored under a name with the {\tt select -set <name>}
command. The stored selections can be used in later select expressions
using the syntax {\tt @<name>}.
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
select -set cone_a state_a %ci*:-$dff # set @cone_a to the input cone of state_a
select -set cone_b state_b %ci*:-$dff # set @cone_b to the input cone of state_b
select @cone_a @cone_b %i # select the objects that are in both cones
\end{lstlisting}
\bigskip
Remember that select expressions can also be used directly as arguments to most
commands. Some commands also except a single select argument to some options.
In those cases selection variables must be used to capture more complex selections.
\medskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
dump @cone_a @cone_b
select -set cone_ab @cone_a @cone_b %i
show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
\end{lstlisting}
\end{frame}
\begin{frame}[fragile]{\subsubsecname{} -- Example}
\begin{columns}
\column[t]{4cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select.v}
\column[t]{7cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select.ys}
\end{columns}
\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Advanced uses of techmap}
\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}
\subsubsection{Introduction to techmap}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item
The {\tt techmap} command replaces cells in the design with implementations given
as Verilog code (called ``map files''). It can replace Yosys' internal cell
types (such as {\tt \$or}) as well as user-defined cell types.
\medskip\item
Verilog parameters are used extensively to customize the internal cell types.
\medskip\item
Additional special parameters are used by techmap to communicate meta-data to the
map files.
\medskip\item
Special wires are used to instruct techmap how to handle a module in the map file.
\medskip\item
Generate blocks and recursion are powerful tools for writing map files.
\end{itemize}
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example 1/2}
\vskip-0.2cm
To map the Verilog OR-reduction operator to 3-input OR gates:
\vskip-0.2cm
\begin{columns}
\column[t]{0.35\linewidth}
\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=24]{PRESENTATION_ExAdv/red_or3x1_map.v}
\column[t]{0.65\linewidth}
\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=25]{PRESENTATION_ExAdv/red_or3x1_map.v}
\end{columns}
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example 2/2}
\vbox to 0cm{
\hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf}
\vss
}
\begin{columns}
\column[t]{6cm}
\column[t]{4cm}
\vskip-0.6cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, firstline=4, lastline=4, frame=single]{PRESENTATION_ExAdv/red_or3x1_test.ys}
\vskip-0.2cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/red_or3x1_test.v}
\end{columns}
\end{frame}
\subsubsection{Conditional techmap}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item In some cases only cells with certain properties should be substituted.
\medskip
\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module
in the map file for a certain set of parameters.
\medskip
\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it
is non-zero then the module is disabled for this set of parameters.
\medskip
\item Example use-cases:
\begin{itemize}
\item coarse-grain cell types that only operate on certain bit widths
\item memory resources for different memory geometries (width, depth, ports, etc.)
\end{itemize}
\end{itemize}
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip-0.5cm
\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf}
\vss
}
\vskip-0.5cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v}
\begin{columns}
\column[t]{6cm}
\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v}
\column[t]{4cm}
\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys}
\end{columns}
\end{frame}
\subsubsection{Scripting in map modules}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
in the context of the replacement module.
\medskip
\item The wire that comes first in alphabetical oder is interpreted as string (must
be connected to constants) that is executed as script. Then the wire is removed. Repeat.
\medskip
\item You can even call techmap recursively!
\medskip
\item Example use-cases:
\begin{itemize}
\item Using always blocks in map module: call {\tt proc}
\item Perform expensive optimizations (such as {\tt freduce}) on cells where
this is known to work well.
\item Interacting with custom commands.
\end{itemize}
\end{itemize}
\scriptsize
PROTIP: Commands such as {\tt shell}, {\tt show -pause}, and {\tt dump} can be use
in the {\tt \_TECHMAP\_DO\_*} scripts for debugging map modules.
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip4.2cm
\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys}
\end{columns}
\end{frame}
\subsubsection{Handling constant inputs}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item The special parameters {\tt \_TECHMAP\_CONSTMSK\_\it <port-name>\tt \_} and
{\tt \_TECHMAP\_CONSTVAL\_\it <port-name>\tt \_} can be used to handle constant
input values to cells.
\medskip
\item The former contains 1-bits for all constant input bits on the port.
\medskip
\item The latter contains the constant bits or undef (x) for non-constant bits.
\medskip
\item Example use-cases:
\begin{itemize}
\item Converting arithmetic (for example multiply to shift)
\item Identify constant addresses or enable bits in memory interfaces.
\end{itemize}
\end{itemize}
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip5.2cm
\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mulshift.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.4cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mulshift_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mulshift_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mulshift_test.ys}
\end{columns}
\end{frame}
\subsubsection{Handling shorted inputs}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
\medskip
\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
\medskip
\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
\medskip
\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
\medskip
\item Example use-cases:
\begin{itemize}
\item Detecting shared clock or control signals in memory interfaces.
\item In some cases this can be used for for optimization.
\end{itemize}
\end{itemize}
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip4.5cm
\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.4cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
\end{columns}
\end{frame}
\subsubsection{Notes on using techmap}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item Don't use positional cell parameters in map modules.
\medskip
\item Don't try to implement basic logic optimization with techmap. \\
{\small (So the OR-reduce using OR3X1 cells map was actually a bad example.)}
\medskip
\item You can use the {\tt \$\_\,\_}-prefix for internal cell types to avoid
collisions with the user-namespace. But always use two underscores or the
internal consistency checker will trigger on this cells.
\medskip
\item Techmap has two major use cases:
\begin{itemize}
\item Creating good logic-level representation of arithmetic functions. \\
This also means using dedicated hardware resources such as half- and full-adder
cells in ASICS or dedicated carry logic in FPGAs.
\smallskip
\item Mapping of coarse-grain resources such as block memory or DSP cells.
\end{itemize}
\end{itemize}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Coarse-grain synthesis}
\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}
\subsubsection{Intro to coarse-grain synthesis}
\begin{frame}[fragile]{\subsubsecname}
In coarse-grain synthesis the target architecture has cells of the same
complexity or larger complexity than the internal RTL representation.
For example:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]
wire [15:0] a, b;
wire [31:0] c, y;
assign y = a * b + c;
\end{lstlisting}
This circuit contains two cells in the RTL representation: one multiplier and
one adder. In some architectures this circuit can be implemented using
a single circuit element, for example an FPGA DSP core. Coarse grain synthesis
is this mapping of groups of circuit elements to larger components.
\bigskip
Fine-grain synthesis would be matching the circuit elements to smaller
components, such as LUTs, gates, or half- and full-adders.
\end{frame}
\subsubsection{The extract pass}
\begin{frame}{\subsubsecname}
\begin{itemize}
\item Like the {\tt techmap} pass, the {\tt extract} pass is called with
a map file. It compares the circuits inside the modules of the map file
with the design and looks for sub-circuits in the design that match any
of the modules in the map file.
\bigskip
\item If a match is found, the {\tt extract} pass will replace the matching
subcircuit with an instance of the module from the map file.
\bigskip
\item In a way the {\tt extract} pass is the inverse of the techmap pass.
\end{itemize}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- Example 1/2}
\vbox to 0cm{
\vskip2cm
\begin{tikzpicture}
\node at (0,0) {\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00a.pdf}};
\node at (3,-3) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_00b.pdf}};
\draw[yshift=0.2cm,thick,-latex] (1,-1) -- (2,-2);
\end{tikzpicture}
\vss}
\vskip-1.2cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/macc_simple_xmap.v}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys]
read_verilog macc_simple_test.v
hierarchy -check -top test
extract -map macc_simple_xmap.v;;
\end{lstlisting}
\end{columns}
\end{frame}
\begin{frame}[fragile]{\subsubsecname{} -- Example 2/2}
\hfil\begin{tabular}{cc}
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_01.v}}} &
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/macc_simple_test_02.v}}} \\
$\downarrow$ & $\downarrow$ \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01a.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02a.pdf}} \\
$\downarrow$ & $\downarrow$ \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_01b.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_simple_test_02b.pdf}} \\
\end{tabular}
\end{frame}
\subsubsection{The wrap-extract-unwrap method}
\begin{frame}{\subsubsecname}
\scriptsize
Often a coarse-grain element has a constant bit-width, but can be used to
implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
can also be used to implement 16x20-bit multiplication.
\bigskip
A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method:
\begin{itemize}
\item {\bf wrap} \\
Identify candidate-cells in the circuit and wrap them in a cell with a constant
wider bit-width using {\tt techmap}. The wrappers use the same parameters as the original cell, so
the information about the original width of the ports is preserved. \\
Then use the {\tt connwrappers} command to connect up the bit-extended in- and
outputs of the wrapper cells.
\item {\bf extract} \\
Now all operations are encoded using the same bit-width as the coarse grain element. The {\tt
extract} command can be used to replace circuits with cells of the target architecture.
\item {\bf unwrap} \\
The remaining wrapper cell can be unwrapped using {\tt techmap}.
\end{itemize}
\bigskip
The following sides detail an example that shows how to map MACC operations of
arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder (such as
the Xilinx DSP48 cells).
\end{frame}
\subsubsection{Example: DSP48\_MACC}
\begin{frame}[t, fragile]{\subsubsecname{} -- 1/13}
Preconditioning: {\tt macc\_xilinx\_swap\_map.v} \\
Make sure {\tt A} is the smaller port on all multipliers
\begin{columns}
\column{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=15]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
\column{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=16]{PRESENTATION_ExAdv/macc_xilinx_swap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 2/13}
Wrapping multipliers: {\tt macc\_xilinx\_wrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, lastline=23]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=24, lastline=46]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 3/13}
Wrapping adders: {\tt macc\_xilinx\_wrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=48, lastline=67]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=68, lastline=89]{PRESENTATION_ExAdv/macc_xilinx_wrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 4/13}
Extract: {\tt macc\_xilinx\_xmap.v}
\lstinputlisting[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_xmap.v}
.. simply use the same wrapping commands on this module as on the design to create a template for the {\tt extract} command.
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 5/13}
Unwrapping multipliers: {\tt macc\_xilinx\_unwrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=1, lastline=17]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=18, lastline=30]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 6/13}
Unwrapping adders: {\tt macc\_xilinx\_unwrap\_map.v}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=32, lastline=48]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog, firstline=49, lastline=61]{PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v}
\end{columns}
\end{frame}
\begin{frame}[fragile]{\subsubsecname{} -- 7/13}
\hfil\begin{tabular}{cc}
{\tt test1} & {\tt test2} \\
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=1, lastline=6, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} &
\fbox{\hbox to 5cm {\lstinputlisting[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, firstline=8, lastline=13, language=verilog]{PRESENTATION_ExAdv/macc_xilinx_test.v}}} \\
$\downarrow$ & $\downarrow$ \\
\end{tabular}
\vskip-0.5cm
\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
read_verilog macc_xilinx_test.v
hierarchy -check
\end{lstlisting}
\vskip-0.5cm
\hfil\begin{tabular}{cc}
$\downarrow$ & $\downarrow$ \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
\end{tabular}
\end{frame}
\begin{frame}[fragile]{\subsubsecname{} -- 8/13}
\hfil\begin{tabular}{cc}
{\tt test1} & {\tt test2} \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1a.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2a.pdf}} \\
$\downarrow$ & $\downarrow$ \\
\end{tabular}
\vskip-0.2cm
\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
techmap -map macc_xilinx_swap_map.v ;;
\end{lstlisting}
\vskip-0.2cm
\hfil\begin{tabular}{cc}
$\downarrow$ & $\downarrow$ \\
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}} &
\fbox{\includegraphics[width=5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}} \\
\end{tabular}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 9/13}
Wrapping in {\tt test1}:
\begin{columns}
\column[t]{5cm}
\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1b.pdf}}\vss}
\column[t]{6cm}
\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
techmap -map macc_xilinx_wrap_map.v
connwrappers -unsigned $__mul_wrapper \
Y Y_WIDTH \
-unsigned $__add_wrapper \
Y Y_WIDTH ;;
\end{lstlisting}
\end{columns}
\vskip1cm
\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 10/13}
Wrapping in {\tt test2}:
\begin{columns}
\column[t]{5cm}
\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2b.pdf}}\vss}
\column[t]{6cm}
\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
techmap -map macc_xilinx_wrap_map.v
connwrappers -unsigned $__mul_wrapper \
Y Y_WIDTH \
-unsigned $__add_wrapper \
Y Y_WIDTH ;;
\end{lstlisting}
\end{columns}
\vskip1cm
\hfil\includegraphics[width=\linewidth,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 11/13}
Extract in {\tt test1}:
\begin{columns}
\column[t]{4.5cm}
\vbox to 0cm{
\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
design -push
read_verilog macc_xilinx_xmap.v
techmap -map macc_xilinx_swap_map.v
techmap -map macc_xilinx_wrap_map.v;;
design -save __macc_xilinx_xmap
design -pop
\end{lstlisting}
\vss}
\column[t]{5.5cm}
\vskip-1cm
\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
extract -constports -ignore_parameters \
-map %__macc_xilinx_xmap \
-swap $__add_wrapper A,B ;;
\end{lstlisting}
\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1c.pdf}}\vss}
\end{columns}
\vskip2cm
\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test1d.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 12/13}
Extract in {\tt test2}:
\begin{columns}
\column[t]{4.5cm}
\vbox to 0cm{
\begin{lstlisting}[linewidth=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
design -push
read_verilog macc_xilinx_xmap.v
techmap -map macc_xilinx_swap_map.v
techmap -map macc_xilinx_wrap_map.v;;
design -save __macc_xilinx_xmap
design -pop
\end{lstlisting}
\vss}
\column[t]{5.5cm}
\vskip-1cm
\begin{lstlisting}[linewidth=5.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
extract -constports -ignore_parameters \
-map %__macc_xilinx_xmap \
-swap $__add_wrapper A,B ;;
\end{lstlisting}
\vbox to 0cm{\fbox{\includegraphics[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2c.pdf}}\vss}
\end{columns}
\vskip2cm
\hfil\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsubsecname{} -- 13/13}
Unwrap in {\tt test2}:
\hfil\begin{tikzpicture}
\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
\node at (0,-4) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
techmap -map macc_xilinx_unwrap_map.v ;;
\end{lstlisting}};
\draw[-latex] (4,-0.7) .. controls (5,-1.7) .. (4,-2.7);
\end{tikzpicture}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Automatic design changes}

1
manual/PRESENTATION_ExAdv/.gitignore vendored
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@ -1 +0,0 @@
*.dot

28
manual/PRESENTATION_ExAdv/Makefile
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@ -1,28 +0,0 @@
all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
macc_simple_xmap.pdf macc_xilinx_xmap.pdf
select.pdf: select.v select.ys
../../yosys select.ys
red_or3x1.pdf: red_or3x1_*
../../yosys red_or3x1_test.ys
sym_mul.pdf: sym_mul_*
../../yosys sym_mul_test.ys
mymul.pdf: mymul_*
../../yosys mymul_test.ys
mulshift.pdf: mulshift_*
../../yosys mulshift_test.ys
addshift.pdf: addshift_*
../../yosys addshift_test.ys
macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
../../yosys macc_simple_test.ys
macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
../../yosys macc_xilinx_test.ys

20
manual/PRESENTATION_ExAdv/addshift_map.v
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@ -1,20 +0,0 @@
module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
parameter _TECHMAP_CONNMAP_B_ = 0;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
assign Y = A << 1;
endmodule

5
manual/PRESENTATION_ExAdv/addshift_test.v
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@ -1,5 +0,0 @@
module test (A, B, X, Y);
input [7:0] A, B;
output [7:0] X = A + B;
output [7:0] Y = A + A;
endmodule

6
manual/PRESENTATION_ExAdv/addshift_test.ys
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@ -1,6 +0,0 @@
read_verilog addshift_test.v
hierarchy -check -top test
techmap -map addshift_map.v;;
show -prefix addshift -format pdf -notitle

6
manual/PRESENTATION_ExAdv/macc_simple_test.v
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@ -1,6 +0,0 @@
module test(a, b, c, d, y);
input [15:0] a, b;
input [31:0] c, d;
output [31:0] y;
assign y = a * b + c + d;
endmodule

37
manual/PRESENTATION_ExAdv/macc_simple_test.ys
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@ -1,37 +0,0 @@
read_verilog macc_simple_test.v
hierarchy -check -top test;;
show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
extract -constports -map macc_simple_xmap.v;;
show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_test_01.v
hierarchy -check -top test;;
show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
extract -map macc_simple_xmap.v;;
show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_test_02.v
hierarchy -check -top test;;
show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
extract -map macc_simple_xmap.v;;
show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_xmap.v
hierarchy -check -top macc_16_16_32;;
show -prefix macc_simple_xmap -format pdf -notitle

6
manual/PRESENTATION_ExAdv/macc_simple_test_01.v
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@ -1,6 +0,0 @@
module test(a, b, c, d, x, y);
input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + c*d + x;
endmodule

6
manual/PRESENTATION_ExAdv/macc_simple_test_02.v
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@ -1,6 +0,0 @@
module test(a, b, c, d, x, y);
input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + (c*d + x);
endmodule

6
manual/PRESENTATION_ExAdv/macc_simple_xmap.v
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@ -1,6 +0,0 @@
module macc_16_16_32(a, b, c, y);
input [15:0] a, b;
input [31:0] c;
output [31:0] y;
assign y = a*b + c;
endmodule

28
manual/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
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@ -1,28 +0,0 @@
(* techmap_celltype = "$mul" *)
module mul_swap_ports (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
\$mul #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(B),
.B(A),
.Y(Y)
);
endmodule

13
manual/PRESENTATION_ExAdv/macc_xilinx_test.v
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@ -1,13 +0,0 @@
module test1(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + c*d + e*f;
endmodule
module test2(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + (c*d + e*f);
endmodule

43
manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
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@ -1,43 +0,0 @@
read_verilog macc_xilinx_test.v
read_verilog -lib -icells macc_xilinx_unwrap_map.v
read_verilog -lib -icells macc_xilinx_xmap.v
hierarchy -check ;;
show -prefix macc_xilinx_test1a -format pdf -notitle test1
show -prefix macc_xilinx_test2a -format pdf -notitle test2
techmap -map macc_xilinx_swap_map.v;;
show -prefix macc_xilinx_test1b -format pdf -notitle test1
show -prefix macc_xilinx_test2b -format pdf -notitle test2
techmap -map macc_xilinx_wrap_map.v
connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
-unsigned $__add_wrapper Y Y_WIDTH;;
show -prefix macc_xilinx_test1c -format pdf -notitle test1
show -prefix macc_xilinx_test2c -format pdf -notitle test2
design -push
read_verilog macc_xilinx_xmap.v
techmap -map macc_xilinx_swap_map.v
techmap -map macc_xilinx_wrap_map.v;;
design -save __macc_xilinx_xmap
design -pop
extract -constports -ignore_parameters \
-map %__macc_xilinx_xmap \
-swap $__add_wrapper A,B ;;
show -prefix macc_xilinx_test1d -format pdf -notitle test1
show -prefix macc_xilinx_test2d -format pdf -notitle test2
techmap -map macc_xilinx_unwrap_map.v;;
show -prefix macc_xilinx_test1e -format pdf -notitle test1
show -prefix macc_xilinx_test2e -format pdf -notitle test2
design -load __macc_xilinx_xmap
show -prefix macc_xilinx_xmap -format pdf -notitle

61
manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
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@ -1,61 +0,0 @@
module \$__mul_wrapper (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [17:0] A;
input [24:0] B;
output [47:0] Y;
wire [A_WIDTH-1:0] A_ORIG = A;
wire [B_WIDTH-1:0] B_ORIG = B;
wire [Y_WIDTH-1:0] Y_ORIG;
assign Y = Y_ORIG;
\$mul #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A_ORIG),
.B(B_ORIG),
.Y(Y_ORIG)
);
endmodule
module \$__add_wrapper (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [47:0] A;
input [47:0] B;
output [47:0] Y;
wire [A_WIDTH-1:0] A_ORIG = A;
wire [B_WIDTH-1:0] B_ORIG = B;
wire [Y_WIDTH-1:0] Y_ORIG;
assign Y = Y_ORIG;
\$add #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A_ORIG),
.B(B_ORIG),
.Y(Y_ORIG)
);
endmodule

89
manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
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@ -1,89 +0,0 @@
(* techmap_celltype = "$mul" *)
module mul_wrap (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [17:0] A_18 = A;
wire [24:0] B_25 = B;
wire [47:0] Y_48;
assign Y = Y_48;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
reg _TECHMAP_FAIL_;
initial begin
_TECHMAP_FAIL_ <= 0;
if (A_SIGNED || B_SIGNED)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH < 4 || B_WIDTH < 4)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH > 18 || B_WIDTH > 25)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH*B_WIDTH < 100)
_TECHMAP_FAIL_ <= 1;
end
\$__mul_wrapper #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A_18),
.B(B_25),
.Y(Y_48)
);
endmodule
(* techmap_celltype = "$add" *)
module add_wrap (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [47:0] A_48 = A;
wire [47:0] B_48 = B;
wire [47:0] Y_48;
assign Y = Y_48;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
reg _TECHMAP_FAIL_;
initial begin
_TECHMAP_FAIL_ <= 0;
if (A_SIGNED || B_SIGNED)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH < 10 && B_WIDTH < 10)
_TECHMAP_FAIL_ <= 1;
end
\$__add_wrapper #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A_48),
.B(B_48),
.Y(Y_48)
);
endmodule

10
manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
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@ -1,10 +0,0 @@
module DSP48_MACC (a, b, c, y);
input [17:0] a;
input [24:0] b;
input [47:0] c;
output [47:0] y;
assign y = a*b + c;
endmodule

26
manual/PRESENTATION_ExAdv/mulshift_map.v
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@ -1,26 +0,0 @@
module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output reg [WIDTH-1:0] Y;
parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
reg _TECHMAP_FAIL_;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
integer i;
always @* begin
_TECHMAP_FAIL_ <= 1;
for (i = 0; i < WIDTH; i=i+1) begin
if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
_TECHMAP_FAIL_ <= 0;
Y <= B << i;
end
if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
_TECHMAP_FAIL_ <= 0;
Y <= A << i;
end
end
end
endmodule

5
manual/PRESENTATION_ExAdv/mulshift_test.v
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@ -1,5 +0,0 @@
module test (A, X, Y);
input [7:0] A;
output [7:0] X = A * 8'd 6;
output [7:0] Y = A * 8'd 8;
endmodule

7
manual/PRESENTATION_ExAdv/mulshift_test.ys
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read_verilog mulshift_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v \
-map mulshift_map.v;;
show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v

15
manual/PRESENTATION_ExAdv/mymul_map.v
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module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output reg [WIDTH-1:0] Y;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
integer i;
always @* begin
Y = 0;
for (i = 0; i < WIDTH; i=i+1)
if (A[i])
Y = Y + (B << i);
end
endmodule

4
manual/PRESENTATION_ExAdv/mymul_test.v
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module test(A, B, Y);
input [1:0] A, B;
output [1:0] Y = A * B;
endmodule

15
manual/PRESENTATION_ExAdv/mymul_test.ys
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@ -1,15 +0,0 @@
read_verilog mymul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v \
-map mymul_map.v;;
rename test test_mapped
read_verilog mymul_test.v
miter -equiv test test_mapped miter
flatten miter
sat -verify -prove trigger 0 miter
splitnets -ports test_mapped/A
show -prefix mymul -format pdf -notitle test_mapped

5
manual/PRESENTATION_ExAdv/red_or3x1_cells.v
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module OR3X1(A, B, C, Y);
input A, B, C;
output Y;
assign Y = A | B | C;
endmodule

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manual/PRESENTATION_ExAdv/red_or3x1_map.v
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module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
function integer min;
input integer a, b;
begin
if (a < b)
min = a;
else
min = b;
end
endfunction
genvar i;
generate begin
if (A_WIDTH == 0) begin
assign Y = 0;
end
if (A_WIDTH == 1) begin
assign Y = A;
end
if (A_WIDTH == 2) begin
wire ybuf;
OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
assign Y = ybuf;
end
if (A_WIDTH == 3) begin
wire ybuf;
OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
assign Y = ybuf;
end
if (A_WIDTH > 3) begin
localparam next_stage_sz = (A_WIDTH+2) / 3;
wire [next_stage_sz-1:0] next_stage;
for (i = 0; i < next_stage_sz; i = i+1) begin
localparam bits = min(A_WIDTH - 3*i, 3);
assign next_stage[i] = |A[3*i +: bits];
end
assign Y = |next_stage;
end
end endgenerate
endmodule

5
manual/PRESENTATION_ExAdv/red_or3x1_test.v
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module test (A, Y);
input [6:0] A;
output Y;
assign Y = |A;
endmodule

7
manual/PRESENTATION_ExAdv/red_or3x1_test.ys
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@ -1,7 +0,0 @@
read_verilog red_or3x1_test.v
hierarchy -check -top test
techmap -map red_or3x1_map.v;;
splitnets -ports
show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v

15
manual/PRESENTATION_ExAdv/select.v
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module test(clk, s, a, y);
input clk, s;
input [15:0] a;
output [15:0] y;
reg [15:0] b, c;
always @(posedge clk) begin
b <= a;
c <= b;
end
wire [15:0] state_a = (a ^ b) + c;
wire [15:0] state_b = (a ^ b) - c;
assign y = !s ? state_a : state_b;
endmodule

10
manual/PRESENTATION_ExAdv/select.ys
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read_verilog select.v
hierarchy -check -top test
proc; opt
cd test
select -set cone_a state_a %ci*:-$dff
select -set cone_b state_b %ci*:-$dff
select -set cone_ab @cone_a @cone_b %i
show -prefix select -format pdf -notitle \
-color red @cone_ab -color magenta @cone_a \
-color blue @cone_b

6
manual/PRESENTATION_ExAdv/sym_mul_cells.v
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module MYMUL(A, B, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
assign Y = A * B;
endmodule

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manual/PRESENTATION_ExAdv/sym_mul_map.v
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module \$mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
endmodule

5
manual/PRESENTATION_ExAdv/sym_mul_test.v
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module test(A, B, C, Y1, Y2);
input [7:0] A, B, C;
output [7:0] Y1 = A * B;
output [15:0] Y2 = A * C;
endmodule

6
manual/PRESENTATION_ExAdv/sym_mul_test.ys
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read_verilog sym_mul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v;;
show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v

227
manual/PRESENTATION_ExOth.tex
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\section{Yosys by example -- Beyond Synthesis}
\begin{frame}
\sectionpage
\end{frame}
\begin{frame}{Overview}
This section contains 2 subsections:
\begin{itemize}
\item Interactive Design Investigation
\item Symbolic Model Checking
\end{itemize}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Interactive Design Investigation}
\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}
\begin{frame}{\subsecname}
Yosys can also be used to investigate designs (or netlists created
from other tools).
\begin{itemize}
\item
The selection mechanism (see slides ``Using Selections''), especially patterns such
as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
are connected.
\item
Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
to transform the design into an equivalent design that is easier to analyse.
\item
Commands such as {\tt eval} and {\tt sat} can be used to investigate the
behavior of the circuit.
\end{itemize}
\end{frame}
\begin{frame}[t, fragile]{Example: Reorganizing a module}
\begin{columns}
\column[t]{4cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExOth/scrambler.v}
\column[t]{7cm}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
read_verilog scrambler.v
hierarchy; proc;;
cd scrambler
submod -name xorshift32 \
xs %c %ci %D %c %ci:+[D] %D \
%ci*:-$dff xs %co %ci %d
\end{lstlisting}
\end{columns}
\hfil\includegraphics[width=11cm,trim=0 0cm 0 1.5cm]{PRESENTATION_ExOth/scrambler_p01.pdf}
\hfil\includegraphics[width=11cm,trim=0 0cm 0 2cm]{PRESENTATION_ExOth/scrambler_p02.pdf}
\end{frame}
\begin{frame}[t, fragile]{Example: Analysis of circuit behavior}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
> read_verilog scrambler.v
> hierarchy; proc;; cd scrambler
> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
> cd xorshift32
> rename n2 in
> rename n1 out
> eval -set in 1 -show out
Eval result: \out = 270369.
> eval -set in 270369 -show out
Eval result: \out = 67634689.
> sat -set out 632435482
Signal Name Dec Hex Bin
-------------------- ---------- ---------- -------------------------------------
\in 745495504 2c6f5bd0 00101100011011110101101111010000
\out 632435482 25b2331a 00100101101100100011001100011010
\end{lstlisting}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Symbolic Model Checking}
\begin{frame}
\subsectionpage
\subsectionpagesuffix
\end{frame}
\begin{frame}{\subsecname}
Symbolic Model Checking (SMC) is used to formally prove that a circuit has
(or has not) a given property.
\bigskip
One application is Formal Equivalence Checking: Proving that two circuits
are identical. For example this is a very useful feature when debugging custom
passes in Yosys.
\bigskip
Other applications include checking if a module conforms to interface
standards.
\bigskip
The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking.
\end{frame}
\begin{frame}[t]{Example: Formal Equivalence Checking (1/2)}
Remember the following example?
\vskip1em
\vbox to 0cm{
\vskip-0.3cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/techmap_01_map.v}
}\vbox to 0cm{
\vskip-0.5cm
\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExSyn/techmap_01.v}
\lstinputlisting[xleftmargin=5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExSyn/techmap_01.ys}}
\vskip5cm\hskip5cm
Lets see if it is correct..
\end{frame}
\begin{frame}[t, fragile]{Example: Formal Equivalence Checking (2/2)}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
# read test design
read_verilog techmap_01.v
hierarchy -top test
# create two version of the design: test_orig and test_mapped
copy test test_orig
rename test test_mapped
# apply the techmap only to test_mapped
techmap -map techmap_01_map.v test_mapped
# create a miter circuit to test equivalence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
# run equivalence check
sat -verify -prove-asserts -show-inputs -show-outputs miter
\end{lstlisting}
\dots
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
Solving problem with 945 variables and 2505 clauses..
SAT proof finished - no model found: SUCCESS!
\end{lstlisting}
\end{frame}
\begin{frame}[t, fragile]{Example: Symbolic Model Checking (1/2)}
\small
The following AXI4 Stream Master has a bug. But the bug is not exposed if the
slave keeps {\tt tready} asserted all the time. (Something a test bench might do.)
\medskip
Symbolic Model Checking can be used to expose the bug and find a sequence
of values for {\tt tready} that yield the incorrect behavior.
\vskip-1em
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_master.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{5pt}{6pt}\selectfont, language=verilog]{PRESENTATION_ExOth/axis_test.v}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{Example: Symbolic Model Checking (2/2)}
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
read_verilog -sv axis_master.v axis_test.v
hierarchy -top axis_test
proc; flatten;;
sat -seq 50 -prove-asserts
\end{lstlisting}
\bigskip
\dots with unmodified {\tt axis\_master.v}:
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
Solving problem with 159344 variables and 442126 clauses..
SAT proof finished - model found: FAIL!
\end{lstlisting}
\bigskip
\dots with fixed {\tt axis\_master.v}:
\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
Solving problem with 159144 variables and 441626 clauses..
SAT proof finished - no model found: SUCCESS!
\end{lstlisting}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Summary}
\begin{frame}{\subsecname}
\begin{itemize}
\item Yosys provides useful features beyond synthesis.
\item The commands {\tt sat} and {\tt eval} can be used to analyse the behavior of a circuit.
\item The {\tt sat} command can also be used for symbolic model checking.
\item This can be useful for debugging and testing designs and Yosys extensions alike.
\end{itemize}
\bigskip
\bigskip
\begin{center}
Questions?
\end{center}
\bigskip
\bigskip
\begin{center}
\url{https://yosyshq.net/yosys/}
\end{center}
\end{frame}

1
manual/PRESENTATION_ExOth/.gitignore vendored
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*.dot

16
manual/PRESENTATION_ExOth/Makefile
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@ -1,16 +0,0 @@
all: scrambler_p01.pdf scrambler_p02.pdf equiv.log axis_test.log
scrambler_p01.pdf: scrambler.ys scrambler.v
../../yosys scrambler.ys
scrambler_p02.pdf: scrambler_p01.pdf
equiv.log: equiv.ys
../../yosys -l equiv.log_new equiv.ys
mv equiv.log_new equiv.log
axis_test.log: axis_test.ys axis_master.v axis_test.v
../../yosys -l axis_test.log_new axis_test.ys
mv axis_test.log_new axis_test.log

27
manual/PRESENTATION_ExOth/axis_master.v
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module axis_master(aclk, aresetn, tvalid, tready, tdata);
input aclk, aresetn, tready;
output reg tvalid;
output reg [7:0] tdata;
reg [31:0] state;
always @(posedge aclk) begin
if (!aresetn) begin
state <= 314159265;
tvalid <= 0;
tdata <= 'bx;
end else begin
if (tvalid && tready)
tvalid <= 0;
if (!tvalid || !tready) begin
// ^- should not be inverted!
state = state ^ state << 13;
state = state ^ state >> 7;
state = state ^ state << 17;
if (state[9:8] == 0) begin
tvalid <= 1;
tdata <= state;
end
end
end
end
endmodule

27
manual/PRESENTATION_ExOth/axis_test.v
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module axis_test(aclk, tready);
input aclk, tready;
wire aresetn, tvalid;
wire [7:0] tdata;
integer counter = 0;
reg aresetn = 0;
axis_master uut (aclk, aresetn, tvalid, tready, tdata);
always @(posedge aclk) begin
if (aresetn && tready && tvalid) begin
if (counter == 0) assert(tdata == 19);
if (counter == 1) assert(tdata == 99);
if (counter == 2) assert(tdata == 1);
if (counter == 3) assert(tdata == 244);
if (counter == 4) assert(tdata == 133);
if (counter == 5) assert(tdata == 209);
if (counter == 6) assert(tdata == 241);
if (counter == 7) assert(tdata == 137);
if (counter == 8) assert(tdata == 176);
if (counter == 9) assert(tdata == 6);
counter <= counter + 1;
end
aresetn <= 1;
end
endmodule

5
manual/PRESENTATION_ExOth/axis_test.ys
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read_verilog -sv axis_master.v axis_test.v
hierarchy -top axis_test
proc; flatten;;
sat -falsify -seq 50 -prove-asserts

17
manual/PRESENTATION_ExOth/equiv.ys
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# read test design
read_verilog ../PRESENTATION_ExSyn/techmap_01.v
hierarchy -top test
# create two version of the design: test_orig and test_mapped
copy test test_orig
rename test test_mapped
# apply the techmap only to test_mapped
techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
# create a miter circuit to test equivalence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
# run equivalence check
sat -verify -prove-asserts -show-inputs -show-outputs miter

14
manual/PRESENTATION_ExOth/scrambler.v
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module scrambler(
input clk, rst, in_bit,
output reg out_bit
);
reg [31:0] xs;
always @(posedge clk) begin
if (rst)
xs = 1;
xs = xs ^ (xs << 13);
xs = xs ^ (xs >> 17);
xs = xs ^ (xs << 5);
out_bit <= in_bit ^ xs[0];
end
endmodule

23
manual/PRESENTATION_ExOth/scrambler.ys
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read_verilog scrambler.v
hierarchy; proc;;
cd scrambler
submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
cd ..
show -prefix scrambler_p01 -format pdf -notitle scrambler
show -prefix scrambler_p02 -format pdf -notitle xorshift32
echo on
cd xorshift32
rename n2 in
rename n1 out
eval -set in 1 -show out
eval -set in 270369 -show out
sat -set out 632435482