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Move (most of) ExOth and ExAdv slides

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Krystine Sherwin 2023-08-07 12:58:40 +12:00
parent 7ab051778e
commit 8ade2182b0
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docs/resources/PRESENTATION_ExAdv/select.v Normal file
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module test(clk, s, a, y);
input clk, s;
input [15:0] a;
output [15:0] y;
reg [15:0] b, c;
always @(posedge clk) begin
b <= a;
c <= b;
end
wire [15:0] state_a = (a ^ b) + c;
wire [15:0] state_b = (a ^ b) - c;
assign y = !s ? state_a : state_b;
endmodule