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Move (most of) ExOth and ExAdv slides

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Krystine Sherwin 2023-08-07 12:58:40 +12:00
parent 7ab051778e
commit 8ade2182b0
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docs/resources/PRESENTATION_ExAdv/mymul_test.ys Normal file
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read_verilog mymul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v \
-map mymul_map.v;;
rename test test_mapped
read_verilog mymul_test.v
miter -equiv test test_mapped miter
flatten miter
sat -verify -prove trigger 0 miter
splitnets -ports test_mapped/A
show -prefix mymul -format pdf -notitle test_mapped