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This commit is contained in:
Emil J. Tywoniak 2026-06-09 20:29:33 +02:00
parent 2117af318c
commit 8ab96a4285
5 changed files with 335 additions and 119 deletions
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25
kernel/newcelltypes.h
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@ -22,7 +22,7 @@ struct CellTableBuilder {
std::array<TwineRef, MAX_PORTS> ports{};
size_t count = 0;
constexpr PortList() = default;
constexpr PortList(std::initializer_list<TwineRef> init) {
constexpr PortList(std::initializer_list<TW> init) {
for (auto p : init) {
ports[count++] = p;
}
@ -57,7 +57,7 @@ struct CellTableBuilder {
std::array<CellInfo, MAX_CELLS> cells{};
size_t count = 0;
constexpr void setup_type(RTLIL::IdString type, std::initializer_list<TwineRef> inputs, std::initializer_list<TwineRef> outputs, const Features& features) {
constexpr void setup_type(RTLIL::IdString type, std::initializer_list<TW> inputs, std::initializer_list<TW> outputs, const Features& features) {
cells[count++] = {type, PortList(inputs), PortList(outputs), features};
}
constexpr void setup_internals_other()
@ -418,7 +418,7 @@ struct CellTableBuilder {
};
constexpr CellTableBuilder builder{};
constexpr CellTableBuilder builder {};
struct PortInfo {
struct PortLists {
@ -548,7 +548,7 @@ namespace {
struct NewCellType {
RTLIL::IdString type;
pool<RTLIL::IdString> inputs, outputs;
pool<TwineRef> inputs, outputs;
bool is_evaluable;
bool is_combinatorial;
bool is_synthesizable;
@ -582,18 +582,18 @@ struct NewCellTypes {
}
void setup_module(RTLIL::Module *module) {
pool<RTLIL::IdString> inputs, outputs;
pool<TwineRef> inputs, outputs;
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->name);
inputs.insert(wire->meta_->name_id);
if (wire->port_output)
outputs.insert(wire->name);
outputs.insert(wire->meta_->name_id);
}
setup_type(module->name, inputs, outputs);
}
void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) {
void setup_type(RTLIL::IdString type, const pool<TwineRef> &inputs, const pool<TwineRef> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) {
NewCellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};
custom_cell_types[ct.type] = ct;
}
@ -609,6 +609,7 @@ struct NewCellTypes {
bool cell_output(const RTLIL::IdString &type, TwineRef port) const
{
// TODO refactor
if (static_cell_types(type) && StaticCellTypes::port_info.outputs(type).contains(port)) {
return true;
}
@ -618,19 +619,19 @@ struct NewCellTypes {
bool cell_input(const RTLIL::IdString &type, TwineRef port) const
{
if (static_cell_types(type) && StaticCellTypes::port_info.inputs(type).contains(port)) {
if (static_cell_types(type) && StaticCellTypes::port_info.inputs(type).contains(static_to_offset(port))) {
return true;
}
auto it = custom_cell_types.find(type);
return it != custom_cell_types.end() && it->second.inputs.count(port) != 0;
}
RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const
RTLIL::PortDir cell_port_dir(RTLIL::IdString type, TwineRef port) const
{
bool is_input, is_output;
if (static_cell_types(type)) {
is_input = StaticCellTypes::port_info.inputs(type).contains(port);
is_output = StaticCellTypes::port_info.outputs(type).contains(port);
is_input = StaticCellTypes::port_info.inputs(type).contains(static_to_offset(port));
is_output = StaticCellTypes::port_info.outputs(type).contains(static_to_offset(port));
} else {
auto it = custom_cell_types.find(type);
if (it == custom_cell_types.end())