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ast, read_verilog: ownership in AST, use C++ styles for parser and lexer

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This commit is contained in:
Emil J. Tywoniak 2025-06-16 22:55:24 +02:00
parent cd71f190cd
commit 8a9f491ffc
19 changed files with 3295 additions and 3312 deletions
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86
frontends/verilog/verilog_frontend.h
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@ -31,6 +31,13 @@
#include "kernel/yosys.h"
#include "frontends/ast/ast.h"
#include "frontends/verilog/location.hh"
#if ! defined(yyFlexLexerOnce)
#define yyFlexLexer frontend_verilog_yyFlexLexer
#include <FlexLexer.h>
#endif
#include <stdio.h>
#include <stdint.h>
#include <list>
@ -39,62 +46,33 @@ YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND
{
// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
extern struct AST::AstNode *current_ast;
/* Ephemeral context class */
struct ConstParser {
std::optional<std::string> filename;
std::optional<AST::AstSrcLocType> loc;
private:
std::string fmt_maybe_loc(std::string msg);
void log_maybe_loc_error(std::string msg);
void log_maybe_loc_warn(std::string msg);
// divide an arbitrary length decimal number by two and return the rest
int my_decimal_div_by_two(std::vector<uint8_t> &digits);
// find the number of significant bits in a binary number (not including the sign bit)
int my_ilog2(int x);
// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized);
public:
// convert the Verilog code for a constant to an AST node
std::unique_ptr<AST::AstNode> const2ast(std::string code, char case_type = 0, bool warn_z = false);
// this function converts a Verilog constant to an AST_CONSTANT node
AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
// names of locally typedef'ed types in a stack
typedef std::map<std::string, AST::AstNode*> UserTypeMap;
extern std::vector<UserTypeMap> user_type_stack;
// names of package typedef'ed types
extern dict<std::string, AST::AstNode*> pkg_user_types;
// state of `default_nettype
extern bool default_nettype_wire;
// running in SystemVerilog mode
extern bool sv_mode;
// running in -formal mode
extern bool formal_mode;
// running in -noassert mode
extern bool noassert_mode;
// running in -noassume mode
extern bool noassume_mode;
// running in -norestrict mode
extern bool norestrict_mode;
// running in -assume-asserts mode
extern bool assume_asserts_mode;
// running in -assert-assumes mode
extern bool assert_assumes_mode;
// running in -lib mode
extern bool lib_mode;
// running in -specify mode
extern bool specify_mode;
// lexer input stream
extern std::istream *lexin;
}
};
[[noreturn]]
extern void verr_at(std::string filename, int begin_line, char const *fmt, va_list ap);
[[noreturn]]
extern void err_at_loc(frontend_verilog_yy::location loc, char const *fmt, ...);
[[noreturn]]
extern void err_at_ast(AST::AstSrcLocType loc, char const *fmt, ...);
};
YOSYS_NAMESPACE_END
// the usual bison/flex stuff
extern int frontend_verilog_yydebug;
void frontend_verilog_yyerror(char const *fmt, ...);
void frontend_verilog_yyrestart(FILE *f);
int frontend_verilog_yyparse(void);
int frontend_verilog_yylex_destroy(void);
int frontend_verilog_yyget_lineno(void);
void frontend_verilog_yyset_lineno (int);
#endif