mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-18 20:03:39 +00:00
Code Activity

ast, read_verilog: ownership in AST, use C++ styles for parser and lexer

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-06-16 22:55:24 +02:00
parent cd71f190cd
commit 8a9f491ffc
19 changed files with 3295 additions and 3312 deletions
Download patch file Download diff file Expand all files Collapse all files

52
frontends/verilog/const2ast.cc
View file

@ -42,14 +42,35 @@
YOSYS_NAMESPACE_BEGIN
using namespace AST;
using namespace VERILOG_FRONTEND;
std::string ConstParser::fmt_maybe_loc(std::string msg) {
std::string s;
s += filename.value_or("INTERNAL");
if (loc)
s += stringf("%d", loc->first_line);
s += ": ";
s += msg;
return s;
}
void ConstParser::log_maybe_loc_error(std::string msg) {
log_error("%s", fmt_maybe_loc(msg).c_str());
}
void ConstParser::log_maybe_loc_warn(std::string msg) {
log_warning("%s", fmt_maybe_loc(msg).c_str());
}
// divide an arbitrary length decimal number by two and return the rest
static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
int ConstParser::my_decimal_div_by_two(std::vector<uint8_t> &digits)
{
int carry = 0;
for (size_t i = 0; i < digits.size(); i++) {
if (digits[i] >= 10)
log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n");
log_maybe_loc_error("Invalid use of [a-fxz?] in decimal constant.\n");
digits[i] += carry * 10;
carry = digits[i] % 2;
digits[i] /= 2;
@ -60,7 +81,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
}
// find the number of significant bits in a binary number (not including the sign bit)
static int my_ilog2(int x)
int ConstParser::my_ilog2(int x)
{
int ret = 0;
while (x != 0 && x != -1) {
@ -71,7 +92,7 @@ static int my_ilog2(int x)
}
// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
void ConstParser::my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type, bool is_unsized)
{
// all digits in string (MSB at index 0)
std::vector<uint8_t> digits;
@ -102,8 +123,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
int bits_per_digit = my_ilog2(base-1);
for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
if (*it > (base-1) && *it < 0xf0)
log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n",
base-1, base);
log_maybe_loc_error(stringf("Digit larger than %d used in in base-%d constant.\n",
base-1, base));
for (int i = 0; i < bits_per_digit; i++) {
int bitmask = 1 << i;
if (*it == 0xf0)
@ -126,7 +147,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
}
if (is_unsized && (len > len_in_bits))
log_file_error(current_filename, get_line_num(), "Unsized constant must have width of 1 bit, but have %d bits!\n", len);
log_maybe_loc_error(stringf("Unsized constant must have width of 1 bit, but have %d bits!\n", len));
for (len = len - 1; len >= 0; len--)
if (data[len] == State::S1)
@ -140,21 +161,19 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
}
if (len_in_bits == 0)
log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n");
log_maybe_loc_error("Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n");
if (len > len_in_bits)
log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n",
len_in_bits, len, current_filename.c_str(), get_line_num());
log_maybe_loc_warn(stringf("Literal has a width of %d bit, but value requires %d bit.\n",
len_in_bits, len));
}
// convert the Verilog code for a constant to an AST node
AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn_z)
std::unique_ptr<AstNode> ConstParser::const2ast(std::string code, char case_type, bool warn_z)
{
if (warn_z) {
AstNode *ret = const2ast(code, case_type);
auto ret = const2ast(code, case_type);
if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n",
current_filename.c_str(), get_line_num());
log_maybe_loc_warn("Yosys has only limited support for tri-state logic at the moment.\n");
return ret;
}
@ -172,7 +191,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
ch = ch >> 1;
}
}
AstNode *ast = AstNode::mkconst_bits(data, false);
auto ast = AstNode::mkconst_bits(data, false);
ast->str = code;
return ast;
}
@ -245,4 +264,5 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
return NULL;
}
YOSYS_NAMESPACE_END