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https://github.com/YosysHQ/yosys
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ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
This commit is contained in:
Emil J. Tywoniak
parent
cd71f190cd
commit
8a9f491ffc
19 changed files with 3295 additions and 3312 deletions
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@ -85,7 +85,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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set_src_attr(wire, that);
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wire->is_signed = that->is_signed;
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if (that != NULL)
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if (that != nullptr)
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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@ -195,22 +195,22 @@ struct AST_INTERNAL::LookaheadRewriter
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if (node->lookahead) {
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log_assert(node->type == AST_IDENTIFIER);
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if (!lookaheadids.count(node->str)) {
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AstNode *wire = new AstNode(AST_WIRE);
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for (auto c : node->id2ast->children)
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auto wire = std::make_unique<AstNode>(AST_WIRE);
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for (auto& c : node->id2ast->children)
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wire->children.push_back(c->clone());
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wire->fixup_hierarchy_flags();
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wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
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wire->is_logic = true;
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while (wire->simplify(true, 1, -1, false)) { }
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current_ast_mod->children.push_back(wire);
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lookaheadids[node->str] = make_pair(node->id2ast, wire);
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lookaheadids[node->str] = make_pair(node->id2ast, wire.get());
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wire->genRTLIL();
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current_ast_mod->children.push_back(std::move(wire));
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}
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}
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for (auto child : node->children)
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collect_lookaheadids(child);
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for (auto& child : node->children)
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collect_lookaheadids(child.get());
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}
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bool has_lookaheadids(AstNode *node)
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@ -218,8 +218,8 @@ struct AST_INTERNAL::LookaheadRewriter
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if (node->type == AST_IDENTIFIER && lookaheadids.count(node->str) != 0)
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return true;
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for (auto child : node->children)
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if (has_lookaheadids(child))
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for (auto& child : node->children)
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if (has_lookaheadids(child.get()))
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return true;
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return false;
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@ -230,8 +230,8 @@ struct AST_INTERNAL::LookaheadRewriter
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if (node->type == AST_IDENTIFIER && lookaheadids.count(node->str) == 0)
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return true;
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for (auto child : node->children)
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if (has_nonlookaheadids(child))
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for (auto& child : node->children)
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if (has_nonlookaheadids(child.get()))
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return true;
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return false;
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@ -241,16 +241,16 @@ struct AST_INTERNAL::LookaheadRewriter
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{
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if (node->type == AST_ASSIGN_LE)
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{
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if (has_lookaheadids(node->children[0]))
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if (has_lookaheadids(node->children[0].get()))
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{
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if (has_nonlookaheadids(node->children[0]))
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if (has_nonlookaheadids(node->children[0].get()))
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log_error("incompatible mix of lookahead and non-lookahead IDs in LHS expression.\n");
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rewrite_lookaheadids(node->children[0], true);
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rewrite_lookaheadids(node->children[0].get(), true);
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node->type = AST_ASSIGN_EQ;
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}
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rewrite_lookaheadids(node->children[1], lhs);
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rewrite_lookaheadids(node->children[1].get(), lhs);
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return;
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}
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@ -261,21 +261,21 @@ struct AST_INTERNAL::LookaheadRewriter
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lhs = false;
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}
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for (auto child : node->children)
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rewrite_lookaheadids(child, lhs);
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for (auto& child : node->children)
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rewrite_lookaheadids(child.get(), lhs);
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}
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LookaheadRewriter(AstNode *top)
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{
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// top->dumpAst(NULL, "REWRITE-BEFORE> ");
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// top->dumpVlog(NULL, "REWRITE-BEFORE> ");
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// top->dumpAst(nullptr, "REWRITE-BEFORE> ");
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// top->dumpVlog(nullptr, "REWRITE-BEFORE> ");
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AstNode *block = nullptr;
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for (auto c : top->children)
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for (auto& c : top->children)
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if (c->type == AST_BLOCK) {
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log_assert(block == nullptr);
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block = c;
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block = c.get();
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}
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log_assert(block != nullptr);
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@ -284,25 +284,25 @@ struct AST_INTERNAL::LookaheadRewriter
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for (auto it : lookaheadids)
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{
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AstNode *ref_orig = new AstNode(AST_IDENTIFIER);
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auto ref_orig = std::make_unique<AstNode>(AST_IDENTIFIER);
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ref_orig->str = it.second.first->str;
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ref_orig->id2ast = it.second.first;
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ref_orig->was_checked = true;
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AstNode *ref_temp = new AstNode(AST_IDENTIFIER);
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auto ref_temp = std::make_unique<AstNode>(AST_IDENTIFIER);
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ref_temp->str = it.second.second->str;
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ref_temp->id2ast = it.second.second;
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ref_temp->was_checked = true;
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AstNode *init_assign = new AstNode(AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
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AstNode *final_assign = new AstNode(AST_ASSIGN_LE, ref_orig, ref_temp);
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auto init_assign = std::make_unique<AstNode>(AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
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auto final_assign = std::make_unique<AstNode>(AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp));
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block->children.insert(block->children.begin(), init_assign);
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block->children.push_back(final_assign);
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block->children.insert(block->children.begin(), std::move(init_assign));
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block->children.push_back(std::move(final_assign));
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}
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// top->dumpAst(NULL, "REWRITE-AFTER> ");
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// top->dumpVlog(NULL, "REWRITE-AFTER> ");
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// top->dumpAst(nullptr, "REWRITE-AFTER> ");
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// top->dumpVlog(nullptr, "REWRITE-AFTER> ");
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}
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};
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@ -310,7 +310,7 @@ struct AST_INTERNAL::LookaheadRewriter
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struct AST_INTERNAL::ProcessGenerator
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{
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// input and output structures
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AstNode *always;
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std::unique_ptr<AstNode> always;
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RTLIL::SigSpec initSyncSignals;
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RTLIL::Process *proc;
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RTLIL::SigSpec outputSignals;
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@ -341,14 +341,14 @@ struct AST_INTERNAL::ProcessGenerator
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// The most recently assigned $print or $check cell \PRIORITY.
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int last_effect_priority;
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ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), last_effect_priority(0)
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ProcessGenerator(std::unique_ptr<AstNode> a, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(std::move(a)), initSyncSignals(initSyncSignalsArg), last_effect_priority(0)
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{
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// rewrite lookahead references
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LookaheadRewriter la_rewriter(always);
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LookaheadRewriter la_rewriter(always.get());
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// generate process and simple root case
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(always->filename).c_str(), always->location.first_line, autoidx++));
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set_src_attr(proc, always);
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set_src_attr(proc, always.get());
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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always->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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@ -358,13 +358,13 @@ struct AST_INTERNAL::ProcessGenerator
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// create initial temporary signal for all output registers
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RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
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collect_lvalues(subst_lvalue_from, always, true, true);
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collect_lvalues(subst_lvalue_from, always.get(), true, true);
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subst_lvalue_to = new_temp_signal(subst_lvalue_from);
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subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
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bool found_global_syncs = false;
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bool found_anyedge_syncs = false;
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for (auto child : always->children)
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for (auto& child : always->children)
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{
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if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
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child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk)) {
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@ -388,7 +388,7 @@ struct AST_INTERNAL::ProcessGenerator
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// create syncs for the process
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bool found_clocked_sync = false;
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for (auto child : always->children)
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for (auto& child : always->children)
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if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
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if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
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child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute(ID::gclk))
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@ -420,9 +420,9 @@ struct AST_INTERNAL::ProcessGenerator
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}
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// process the AST
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for (auto child : always->children)
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for (auto& child : always->children)
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if (child->type == AST_BLOCK)
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processAst(child);
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processAst(child.get());
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for (auto sync: proc->syncs)
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processMemWrites(sync);
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@ -472,7 +472,7 @@ struct AST_INTERNAL::ProcessGenerator
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for (int i = 0; i < GetSize(chunks); i++)
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{
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RTLIL::SigChunk &chunk = chunks[i];
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if (chunk.wire == NULL)
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if (chunk.wire == nullptr)
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continue;
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std::string wire_name;
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@ -484,7 +484,7 @@ struct AST_INTERNAL::ProcessGenerator
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} while (current_module->wires_.count(wire_name) > 0);
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RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
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set_src_attr(wire, always);
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set_src_attr(wire, always.get());
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chunk.wire = wire;
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chunk.offset = 0;
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@ -499,10 +499,10 @@ struct AST_INTERNAL::ProcessGenerator
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switch (ast->type)
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{
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case AST_CASE:
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for (auto child : ast->children)
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for (auto& child : ast->children)
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if (child != ast->children[0]) {
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log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
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collect_lvalues(reg, child, type_eq, type_le, false);
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collect_lvalues(reg, child.get(), type_eq, type_le, false);
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}
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break;
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@ -511,19 +511,19 @@ struct AST_INTERNAL::ProcessGenerator
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case AST_CONDZ:
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case AST_ALWAYS:
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case AST_INITIAL:
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for (auto child : ast->children)
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for (auto& child : ast->children)
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if (child->type == AST_BLOCK)
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collect_lvalues(reg, child, type_eq, type_le, false);
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collect_lvalues(reg, child.get(), type_eq, type_le, false);
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break;
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case AST_BLOCK:
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for (auto child : ast->children) {
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for (auto& child : ast->children) {
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if (child->type == AST_ASSIGN_EQ && type_eq)
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reg.append(child->children[0]->genRTLIL());
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if (child->type == AST_ASSIGN_LE && type_le)
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reg.append(child->children[0]->genRTLIL());
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if (child->type == AST_CASE || child->type == AST_BLOCK)
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collect_lvalues(reg, child, type_eq, type_le, false);
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collect_lvalues(reg, child.get(), type_eq, type_le, false);
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}
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break;
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@ -583,8 +583,8 @@ struct AST_INTERNAL::ProcessGenerator
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switch (ast->type)
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{
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case AST_BLOCK:
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for (auto child : ast->children)
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processAst(child);
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for (auto& child : ast->children)
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processAst(child.get());
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break;
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case AST_ASSIGN_EQ:
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@ -641,9 +641,9 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
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this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
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RTLIL::CaseRule *default_case = NULL;
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RTLIL::CaseRule *last_generated_case = NULL;
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for (auto child : ast->children)
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RTLIL::CaseRule *default_case = nullptr;
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RTLIL::CaseRule *last_generated_case = nullptr;
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for (auto& child : ast->children)
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{
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if (child == ast->children[0])
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continue;
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@ -657,14 +657,14 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::CaseRule *backup_case = current_case;
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current_case = new RTLIL::CaseRule;
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set_src_attr(current_case, child);
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set_src_attr(current_case, child.get());
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last_generated_case = current_case;
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addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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for (auto node : child->children) {
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for (auto& node : child->children) {
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if (node->type == AST_DEFAULT)
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default_case = current_case;
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else if (node->type == AST_BLOCK)
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processAst(node);
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processAst(node.get());
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else
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current_case->compare.push_back(node->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap()));
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}
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@ -678,7 +678,7 @@ struct AST_INTERNAL::ProcessGenerator
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subst_rvalue_map.restore();
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}
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if (last_generated_case != NULL && ast->get_bool_attribute(ID::full_case) && default_case == NULL) {
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if (last_generated_case != nullptr && ast->get_bool_attribute(ID::full_case) && default_case == nullptr) {
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#if 0
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// this is a valid transformation, but as optimization it is premature.
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// better: add a default case that assigns 'x' to everything, and let later
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@ -690,7 +690,7 @@ struct AST_INTERNAL::ProcessGenerator
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sw->cases.push_back(default_case);
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#endif
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} else {
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if (default_case == NULL) {
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if (default_case == nullptr) {
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default_case = new RTLIL::CaseRule;
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addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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}
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@ -760,7 +760,7 @@ struct AST_INTERNAL::ProcessGenerator
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default_base = 16;
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std::vector<VerilogFmtArg> args;
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for (auto node : ast->children) {
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for (auto& node : ast->children) {
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int width;
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bool is_signed;
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node->detectSignWidth(width, is_signed, nullptr);
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@ -866,8 +866,8 @@ struct AST_INTERNAL::ProcessGenerator
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break;
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default:
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// ast->dumpAst(NULL, "ast> ");
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// current_ast_mod->dumpAst(NULL, "mod> ");
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// ast->dumpAst(nullptr, "ast> ");
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// current_ast_mod->dumpAst(nullptr, "mod> ");
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log_abort();
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}
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}
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@ -876,14 +876,14 @@ struct AST_INTERNAL::ProcessGenerator
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{
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// Maps per-memid AST_MEMWR IDs to indices in the mem_write_actions array.
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dict<std::pair<std::string, int>, int> port_map;
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for (auto child : always->children)
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for (auto& child : always->children)
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if (child->type == AST_MEMWR)
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{
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std::string memid = child->str;
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int portid = child->children[3]->asInt(false);
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int cur_idx = GetSize(sync->mem_write_actions);
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RTLIL::MemWriteAction action;
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set_src_attr(&action, child);
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set_src_attr(&action, child.get());
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action.memid = memid;
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action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap());
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action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid]->width, true, &subst_rvalue_map.stdmap());
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@ -971,11 +971,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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bool sub_sign_hint = true;
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int sub_width_hint = -1;
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int this_width = 0;
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AstNode *range = NULL;
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AstNode *id_ast = NULL;
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AstNode *range = nullptr;
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AstNode *id_ast = nullptr;
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bool local_found_real = false;
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if (found_real == NULL)
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if (found_real == nullptr)
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found_real = &local_found_real;
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switch (type)
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@ -1019,22 +1019,22 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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input_error("Failed to detect width for parameter %s!\n", str.c_str());
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}
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if (children.size() != 0)
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range = children[0];
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range = children[0].get();
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} else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
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if (!id_ast->range_valid) {
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if (id_ast->type == AST_AUTOWIRE)
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this_width = 1;
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else {
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// current_ast_mod->dumpAst(NULL, "mod> ");
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// current_ast_mod->dumpAst(nullptr, "mod> ");
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// log("---\n");
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// id_ast->dumpAst(NULL, "decl> ");
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// dumpAst(NULL, "ref> ");
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// id_ast->dumpAst(nullptr, "decl> ");
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// dumpAst(nullptr, "ref> ");
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input_error("Failed to detect width of signal access `%s'!\n", str.c_str());
|
||||
}
|
||||
} else {
|
||||
this_width = id_ast->range_left - id_ast->range_right + 1;
|
||||
if (children.size() != 0)
|
||||
range = children[0];
|
||||
range = children[0].get();
|
||||
}
|
||||
} else if (id_ast->type == AST_GENVAR) {
|
||||
this_width = 32;
|
||||
|
|
@ -1043,26 +1043,23 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
|
||||
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
|
||||
if (children.size() > 1)
|
||||
range = children[1];
|
||||
range = children[1].get();
|
||||
} else if (id_ast->type == AST_STRUCT_ITEM || id_ast->type == AST_STRUCT || id_ast->type == AST_UNION) {
|
||||
AstNode *tmp_range = make_index_range(id_ast);
|
||||
auto tmp_range = make_index_range(id_ast);
|
||||
this_width = tmp_range->range_left - tmp_range->range_right + 1;
|
||||
delete tmp_range;
|
||||
} else
|
||||
input_error("Failed to detect width for identifier %s!\n", str.c_str());
|
||||
if (range) {
|
||||
if (range->children.size() == 1)
|
||||
this_width = 1;
|
||||
else if (!range->range_valid) {
|
||||
AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero();
|
||||
AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone();
|
||||
auto left_at_zero_ast = children[0]->children[0]->clone_at_zero();
|
||||
auto right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone();
|
||||
while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
|
||||
while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
|
||||
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
|
||||
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
|
||||
delete left_at_zero_ast;
|
||||
delete right_at_zero_ast;
|
||||
} else
|
||||
this_width = range->range_left - range->range_right + 1;
|
||||
sign_hint = false;
|
||||
|
|
@ -1106,7 +1103,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
break;
|
||||
|
||||
case AST_CONCAT:
|
||||
for (auto child : children) {
|
||||
for (auto& child : children) {
|
||||
sub_width_hint = 0;
|
||||
sub_sign_hint = true;
|
||||
child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
|
||||
|
|
@ -1135,7 +1132,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
case AST_BIT_OR:
|
||||
case AST_BIT_XOR:
|
||||
case AST_BIT_XNOR:
|
||||
for (auto child : children)
|
||||
for (auto& child : children)
|
||||
child->detectSignWidthWorker(width_hint, sign_hint, found_real);
|
||||
break;
|
||||
|
||||
|
|
@ -1175,7 +1172,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
case AST_MUL:
|
||||
case AST_DIV:
|
||||
case AST_MOD:
|
||||
for (auto child : children)
|
||||
for (auto& child : children)
|
||||
child->detectSignWidthWorker(width_hint, sign_hint, found_real);
|
||||
break;
|
||||
|
||||
|
|
@ -1216,12 +1213,13 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
width_hint = max(width_hint, sub_width_hint);
|
||||
sign_hint &= sub_sign_hint;
|
||||
};
|
||||
visit_case_expr(children[0]);
|
||||
visit_case_expr(children[0].get());
|
||||
for (size_t i = 1; i < children.size(); i++) {
|
||||
AstNode *child = children[i];
|
||||
for (AstNode *v : child->children)
|
||||
AstNode *child = children[i].get();
|
||||
for (auto& v : child->children) {
|
||||
if (v->type != AST_DEFAULT && v->type != AST_BLOCK)
|
||||
visit_case_expr(v);
|
||||
visit_case_expr(v.get());
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -1269,9 +1267,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
if (func->type != AST_FUNCTION)
|
||||
input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str());
|
||||
const AstNode *wire = nullptr;
|
||||
for (const AstNode *child : func->children)
|
||||
for (const auto& child : func->children)
|
||||
if (child->str == func->str) {
|
||||
wire = child;
|
||||
wire = child.get();
|
||||
break;
|
||||
}
|
||||
log_assert(wire && wire->type == AST_WIRE);
|
||||
|
|
@ -1280,10 +1278,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
if (!wire->children.empty())
|
||||
{
|
||||
log_assert(wire->children.size() == 1);
|
||||
const AstNode *range = wire->children.at(0);
|
||||
const AstNode *range = wire->children.at(0).get();
|
||||
log_assert(range->type == AST_RANGE && range->children.size() == 2);
|
||||
AstNode *left = range->children.at(0)->clone();
|
||||
AstNode *right = range->children.at(1)->clone();
|
||||
auto left = range->children.at(0)->clone();
|
||||
auto right = range->children.at(1)->clone();
|
||||
left->set_in_param_flag(true);
|
||||
right->set_in_param_flag(true);
|
||||
while (left->simplify(true, 1, -1, false)) { }
|
||||
|
|
@ -1292,8 +1290,6 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
input_error("Function %s has non-constant width!",
|
||||
RTLIL::unescape_id(str).c_str());
|
||||
result_width = abs(int(left->asInt(true) - right->asInt(true)));
|
||||
delete left;
|
||||
delete right;
|
||||
}
|
||||
width_hint = max(width_hint, result_width);
|
||||
break;
|
||||
|
|
@ -1306,6 +1302,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
|
|||
for (auto f : log_files)
|
||||
current_scope_ast->dumpAst(f, "verilog-ast> ");
|
||||
input_error("Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
|
||||
|
||||
}
|
||||
|
||||
if (*found_real)
|
||||
|
|
@ -1517,11 +1514,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
// shifter cell is created and the output signal of this cell is returned
|
||||
case AST_IDENTIFIER:
|
||||
{
|
||||
RTLIL::Wire *wire = NULL;
|
||||
RTLIL::Wire *wire = nullptr;
|
||||
RTLIL::SigChunk chunk;
|
||||
bool is_interface = false;
|
||||
|
||||
AST::AstNode *member_node = NULL;
|
||||
AST::AstNode *member_node = nullptr;
|
||||
int add_undef_bits_msb = 0;
|
||||
int add_undef_bits_lsb = 0;
|
||||
|
||||
|
|
@ -1608,14 +1605,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
|
||||
if (!children[0]->range_valid) {
|
||||
AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero();
|
||||
AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone();
|
||||
auto left_at_zero_ast = children[0]->children[0]->clone_at_zero();
|
||||
auto right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone();
|
||||
while (left_at_zero_ast->simplify(true, 1, -1, false)) { }
|
||||
while (right_at_zero_ast->simplify(true, 1, -1, false)) { }
|
||||
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
|
||||
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
|
||||
AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
|
||||
auto fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
|
||||
children[0]->children[1]->clone() : children[0]->children[0]->clone());
|
||||
fake_ast->children[0]->delete_children();
|
||||
if (member_node)
|
||||
|
|
@ -1637,9 +1634,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (GetSize(shift_val) >= 32)
|
||||
fake_ast->children[1]->is_signed = true;
|
||||
RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
|
||||
delete left_at_zero_ast;
|
||||
delete right_at_zero_ast;
|
||||
delete fake_ast;
|
||||
return sig;
|
||||
} else {
|
||||
chunk.width = children[0]->range_left - children[0]->range_right + 1;
|
||||
|
|
@ -2092,7 +2086,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
cell->set_bool_attribute(ID::module_not_derived);
|
||||
|
||||
for (auto it = children.begin(); it != children.end(); it++) {
|
||||
AstNode *child = *it;
|
||||
AstNode *child = it->get();
|
||||
if (child->type == AST_CELLTYPE) {
|
||||
cell->type = child->str;
|
||||
if (flag_icells && cell->type.begins_with("\\$"))
|
||||
|
|
@ -2101,7 +2095,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
if (child->type == AST_PARASET) {
|
||||
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
|
||||
const AstNode *value = child->children[0];
|
||||
const AstNode *value = child->children[0].get();
|
||||
if (value->type == AST_REALVALUE)
|
||||
log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
|
||||
log_id(cell), log_id(paraname), value->realvalue);
|
||||
|
|
@ -2114,7 +2108,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (child->type == AST_ARGUMENT) {
|
||||
RTLIL::SigSpec sig;
|
||||
if (child->children.size() > 0) {
|
||||
AstNode *arg = child->children[0];
|
||||
AstNode *arg = child->children[0].get();
|
||||
int local_width_hint = -1;
|
||||
bool local_sign_hint = false;
|
||||
// don't inadvertently attempt to detect the width of interfaces
|
||||
|
|
@ -2186,16 +2180,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
// use ProcessGenerator for always blocks
|
||||
case AST_ALWAYS: {
|
||||
AstNode *always = this->clone();
|
||||
ProcessGenerator generator(always);
|
||||
auto always = this->clone();
|
||||
ProcessGenerator generator(std::move(always));
|
||||
ignoreThisSignalsInInitial.append(generator.outputSignals);
|
||||
delete always;
|
||||
} break;
|
||||
|
||||
case AST_INITIAL: {
|
||||
AstNode *always = this->clone();
|
||||
ProcessGenerator generator(always, ignoreThisSignalsInInitial);
|
||||
delete always;
|
||||
auto always = this->clone();
|
||||
ProcessGenerator generator(std::move(always), ignoreThisSignalsInInitial);
|
||||
} break;
|
||||
|
||||
case AST_TECALL: {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue