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https://github.com/YosysHQ/yosys
synced 2025-06-19 04:13:39 +00:00
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
This commit is contained in:
Emil J. Tywoniak
parent
cd71f190cd
commit
8a9f491ffc
19 changed files with 3295 additions and 3312 deletions
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@ -39,8 +39,7 @@ using namespace AST_INTERNAL;
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// instantiate global variables (public API)
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namespace AST {
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std::string current_filename;
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void (*set_line_num)(int) = NULL;
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int (*get_line_num)() = NULL;
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bool sv_mode;
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unsigned long long astnodes = 0;
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unsigned long long astnode_count() { return astnodes; }
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}
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@ -192,16 +191,16 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
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if (attributes.count(id) == 0)
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return false;
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AstNode *attr = attributes.at(id);
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if (attr->type != AST_CONSTANT)
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attr->input_error("Attribute `%s' with non-constant value!\n", id.c_str());
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AstNode& attr = *(attributes.at(id));
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if (attr.type != AST_CONSTANT)
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attr.input_error("Attribute `%s' with non-constant value!\n", id.c_str());
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return attr->integer != 0;
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return attr.integer != 0;
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}
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// create new node (AstNode constructor)
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// (the optional child arguments make it easier to create AST trees)
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AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3, AstNode *child4)
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AstNode::AstNode(AstNodeType type, std::unique_ptr<AstNode> child1, std::unique_ptr<AstNode> child2, std::unique_ptr<AstNode> child3, std::unique_ptr<AstNode> child4)
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{
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static unsigned int hashidx_count = 123456789;
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hashidx_count = mkhash_xorshift(hashidx_count);
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@ -239,56 +238,74 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
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in_param = false;
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if (child1)
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children.push_back(child1);
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children.push_back(std::move(child1));
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if (child2)
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children.push_back(child2);
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children.push_back(std::move(child2));
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if (child3)
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children.push_back(child3);
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children.push_back(std::move(child3));
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if (child4)
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children.push_back(child4);
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children.push_back(std::move(child4));
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fixup_hierarchy_flags();
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}
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// create a (deep recursive) copy of a node
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AstNode *AstNode::clone() const
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std::unique_ptr<AstNode> AstNode::clone() const
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{
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AstNode *that = new AstNode;
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*that = *this;
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for (auto &it : that->children)
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it = it->clone();
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for (auto &it : that->attributes)
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it.second = it.second->clone();
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that->set_in_lvalue_flag(false);
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that->set_in_param_flag(false);
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that->fixup_hierarchy_flags(); // fixup to set flags on cloned children
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auto that = std::make_unique<AstNode>(this->type);
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cloneInto(*that.get());
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return that;
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}
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// create a (deep recursive) copy of a node use 'other' as target root node
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void AstNode::cloneInto(AstNode *other) const
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void AstNode::cloneInto(AstNode &other) const
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{
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AstNode *tmp = clone();
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tmp->in_lvalue_from_above = other->in_lvalue_from_above;
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tmp->in_param_from_above = other->in_param_from_above;
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other->delete_children();
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*other = *tmp;
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tmp->children.clear();
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tmp->attributes.clear();
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other->fixup_hierarchy_flags();
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delete tmp;
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other.type = type;
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other.str = str;
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other.bits = bits;
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other.is_input = is_input;
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other.is_output = is_output;
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other.is_reg = is_reg;
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other.is_logic = is_logic;
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other.is_signed = is_signed;
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other.is_string = is_string;
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other.is_wand = is_wand;
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other.is_wor = is_wor;
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other.range_valid = range_valid;
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other.range_swapped = range_swapped;
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other.was_checked = was_checked;
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other.is_unsized = is_unsized;
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other.is_custom_type = is_custom_type;
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other.port_id = port_id,
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other.range_left = range_left,
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other.range_right = range_right;
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other.integer = integer;
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other.realvalue = realvalue;
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other.is_enum = is_enum;
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other.dimensions = dimensions;
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other.unpacked_dimensions = unpacked_dimensions;
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other.id2ast = id2ast;
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other.basic_prep = basic_prep;
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other.lookahead = lookahead;
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other.filename = filename;
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other.location = location;
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other.in_lvalue = in_lvalue;
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other.in_param = in_param;
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// Keep in_lvalue_from_above and in_param_from_above untouched
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other.delete_children();
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for (auto& child : this->children)
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other.children.push_back(child->clone());
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for (auto& [key, val] : this->attributes)
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other.attributes[key] = (val->clone());
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// fixup to set flags on cloned children
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other.fixup_hierarchy_flags();
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}
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// delete all children in this node
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void AstNode::delete_children()
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{
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for (auto &it : children)
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delete it;
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children.clear();
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for (auto &it : attributes)
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delete it.second;
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attributes.clear();
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}
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@ -423,18 +440,18 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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{
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case AST_MODULE:
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fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
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for (auto child : children)
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for (const auto& child : children)
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if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
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fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
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first = false;
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}
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fprintf(f, ");\n");
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for (auto child : children)
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for (const auto& child : children)
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if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_DEFPARAM)
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child->dumpVlog(f, indent + " ");
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else
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rem_children1.push_back(child);
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rem_children1.push_back(child.get());
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for (auto child : rem_children1)
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if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
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@ -470,7 +487,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
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if (is_signed)
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fprintf(f, " signed");
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for (auto child : children) {
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for (const auto& child : children) {
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fprintf(f, " ");
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child->dumpVlog(f, "");
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}
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@ -486,7 +503,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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fprintf(f, "%s" "memory", indent.c_str());
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if (is_signed)
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fprintf(f, " signed");
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for (auto child : children) {
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for (const auto& child : children) {
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fprintf(f, " ");
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child->dumpVlog(f, "");
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if (first)
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@ -500,7 +517,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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if (0) { case AST_MEMINIT: txt = "@meminit@"; }
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if (0) { case AST_MEMWR: txt = "@memwr@"; }
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fprintf(f, "%s%s", indent.c_str(), txt.c_str());
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for (auto child : children) {
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for (const auto& child : children) {
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fprintf(f, first ? "(" : ", ");
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child->dumpVlog(f, "");
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first = false;
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@ -517,7 +534,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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else
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fprintf(f, "[%d:%d]", range_left, range_right);
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} else {
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for (auto child : children) {
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for (const auto& child : children) {
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fprintf(f, "%c", first ? '[' : ':');
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child->dumpVlog(f, "");
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first = false;
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@ -527,13 +544,13 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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break;
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case AST_MULTIRANGE:
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for (auto child : children)
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for (const auto& child : children)
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child->dumpVlog(f, "");
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break;
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case AST_ALWAYS:
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fprintf(f, "%s" "always @", indent.c_str());
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for (auto child : children) {
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for (const auto& child : children) {
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if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
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continue;
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fprintf(f, first ? "(" : ", ");
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@ -541,7 +558,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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first = false;
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}
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fprintf(f, first ? "*\n" : ")\n");
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for (auto child : children) {
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for (const auto& child : children) {
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if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
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child->dumpVlog(f, indent + " ");
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}
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@ -549,7 +566,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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case AST_INITIAL:
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fprintf(f, "%s" "initial\n", indent.c_str());
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for (auto child : children) {
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for (const auto& child : children) {
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if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
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child->dumpVlog(f, indent + " ");
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}
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@ -562,7 +579,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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fprintf(f, "posedge ");
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if (type == AST_NEGEDGE)
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fprintf(f, "negedge ");
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for (auto child : children)
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for (const auto& child : children)
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child->dumpVlog(f, "");
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break;
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@ -574,7 +591,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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else
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fprintf(f, "%s", id2vl(str).c_str());
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}
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for (auto child : children)
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for (const auto& child : children)
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child->dumpVlog(f, "");
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break;
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@ -602,7 +619,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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children[0]->dumpVlog(f, indent);
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} else {
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fprintf(f, "%s" "begin\n", indent.c_str());
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for (auto child : children)
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for (const auto& child : children)
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child->dumpVlog(f, indent + " ");
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fprintf(f, "%s" "end\n", indent.c_str());
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}
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@ -618,7 +635,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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children[0]->dumpVlog(f, "");
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fprintf(f, ")\n");
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for (size_t i = 1; i < children.size(); i++) {
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AstNode *child = children[i];
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const auto& child = children[i];
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child->dumpVlog(f, indent + " ");
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}
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fprintf(f, "%s" "endcase\n", indent.c_str());
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@ -627,7 +644,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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case AST_COND:
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case AST_CONDX:
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case AST_CONDZ:
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for (auto child : children) {
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for (const auto& child : children) {
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if (child->type == AST_BLOCK) {
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fprintf(f, ":\n");
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child->dumpVlog(f, indent + " ");
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@ -663,7 +680,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
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case AST_CONCAT:
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fprintf(f, "{");
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for (int i = GetSize(children)-1; i >= 0; i--) {
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auto child = children[i];
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const auto& child = children[i];
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if (!first)
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fprintf(f, ", ");
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child->dumpVlog(f, "");
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@ -818,16 +835,16 @@ bool AstNode::contains(const AstNode *other) const
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{
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if (this == other)
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return true;
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for (auto child : children)
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for (const auto& child : children)
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if (child->contains(other))
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return true;
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return false;
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}
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// create an AST node for a constant (using a 32 bit int as value)
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AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
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std::unique_ptr<AstNode> AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
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{
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AstNode *node = new AstNode(AST_CONSTANT);
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auto node = std::make_unique<AstNode>(AST_CONSTANT);
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node->integer = v;
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node->is_signed = is_signed;
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for (int i = 0; i < width; i++) {
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@ -841,9 +858,9 @@ AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
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}
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// create an AST node for a constant (using a bit vector as value)
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AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized)
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std::unique_ptr<AstNode> AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized)
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{
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AstNode *node = new AstNode(AST_CONSTANT);
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auto node = std::make_unique<AstNode>(AST_CONSTANT);
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node->is_signed = is_signed;
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node->bits = v;
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for (size_t i = 0; i < 32; i++) {
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@ -859,15 +876,15 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
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return node;
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}
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AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
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std::unique_ptr<AstNode> AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
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{
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return mkconst_bits(v, is_signed, false);
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}
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// create an AST node for a constant (using a string in bit vector form as value)
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AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
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std::unique_ptr<AstNode> AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
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{
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AstNode *node = mkconst_str(RTLIL::Const(v).decode_string());
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auto node = mkconst_str(RTLIL::Const(v).decode_string());
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while (GetSize(node->bits) < GetSize(v))
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node->bits.push_back(RTLIL::State::S0);
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log_assert(node->bits == v);
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@ -875,9 +892,9 @@ AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
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}
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// create an AST node for a constant (using a string as value)
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AstNode *AstNode::mkconst_str(const std::string &str)
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std::unique_ptr<AstNode> AstNode::mkconst_str(const std::string &str)
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{
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AstNode *node;
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std::unique_ptr<AstNode> node;
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// LRM 1364-2005 5.2.3.3 The empty string literal ("") shall be considered
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// equivalent to the ASCII NUL ("\0")
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@ -902,18 +919,19 @@ AstNode *AstNode::mkconst_str(const std::string &str)
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}
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// create a temporary register
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AstNode *AstNode::mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed)
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std::unique_ptr<AstNode> AstNode::mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed)
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{
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AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(range_left, true), mkconst_int(range_right, true)));
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auto wire_owned = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, mkconst_int(range_left, true), mkconst_int(range_right, true)));
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auto* wire = wire_owned.get();
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wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++);
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if (nosync)
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
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wire->is_signed = is_signed;
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wire->is_logic = true;
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mod->children.push_back(wire);
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mod->children.push_back(std::move(wire_owned));
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while (wire->simplify(true, 1, -1, false)) { }
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AstNode *ident = new AstNode(AST_IDENTIFIER);
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auto ident = std::make_unique<AstNode>(AST_IDENTIFIER);
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ident->str = wire->str;
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ident->id2ast = wire;
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@ -967,10 +985,9 @@ RTLIL::Const AstNode::asParaConst() const
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{
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if (type == AST_REALVALUE)
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{
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AstNode *strnode = AstNode::mkconst_str(stringf("%f", realvalue));
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auto strnode = AstNode::mkconst_str(stringf("%f", realvalue));
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RTLIL::Const val = strnode->asAttrConst();
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val.flags |= RTLIL::CONST_FLAG_REAL;
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delete strnode;
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return val;
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}
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@ -1078,7 +1095,7 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
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obj->attributes[ID::src] = ast->loc_string();
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}
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static bool param_has_no_default(const AstNode *param) {
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static bool param_has_no_default(const std::unique_ptr<AstNode> ¶m) {
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const auto &children = param->children;
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log_assert(param->type == AST_PARAMETER);
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log_assert(children.size() <= 2);
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|
|
@ -1086,7 +1103,7 @@ static bool param_has_no_default(const AstNode *param) {
|
|||
(children.size() == 1 && children[0]->type == AST_RANGE);
|
||||
}
|
||||
|
||||
static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
|
||||
static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool defer, std::unique_ptr<AstNode> original_ast = NULL, bool quiet = false)
|
||||
{
|
||||
log_assert(current_scope.empty());
|
||||
log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
|
||||
|
|
@ -1100,15 +1117,15 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
AstModule *module = new AstModule;
|
||||
current_module = module;
|
||||
|
||||
module->ast = NULL;
|
||||
module->ast = nullptr;
|
||||
module->name = ast->str;
|
||||
set_src_attr(module, ast);
|
||||
module->set_bool_attribute(ID::cells_not_processed);
|
||||
|
||||
current_ast_mod = ast;
|
||||
AstNode *ast_before_simplify;
|
||||
std::unique_ptr<AstNode> ast_before_simplify;
|
||||
if (original_ast != NULL)
|
||||
ast_before_simplify = original_ast;
|
||||
ast_before_simplify = std::move(original_ast);
|
||||
else
|
||||
ast_before_simplify = ast->clone();
|
||||
|
||||
|
|
@ -1125,7 +1142,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
|
||||
if (!defer)
|
||||
{
|
||||
for (const AstNode *node : ast->children)
|
||||
for (auto& node : ast->children)
|
||||
if (node->type == AST_PARAMETER && param_has_no_default(node))
|
||||
node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str());
|
||||
|
||||
|
|
@ -1133,7 +1150,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
|
||||
if (!blackbox_module && !flag_noblackbox) {
|
||||
blackbox_module = true;
|
||||
for (auto child : ast->children) {
|
||||
for (const auto& child : ast->children) {
|
||||
if (child->type == AST_WIRE && (child->is_input || child->is_output))
|
||||
continue;
|
||||
if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
|
||||
|
|
@ -1163,36 +1180,33 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
ast->dumpVlog(NULL, " ");
|
||||
log("--- END OF AST DUMP ---\n");
|
||||
}
|
||||
|
||||
for (auto &attr: ast->attributes)
|
||||
log_assert((bool)attr.second.get());
|
||||
if (flag_nowb && ast->attributes.count(ID::whitebox)) {
|
||||
delete ast->attributes.at(ID::whitebox);
|
||||
ast->attributes.erase(ID::whitebox);
|
||||
}
|
||||
|
||||
for (auto &attr: ast->attributes)
|
||||
log_assert((bool)attr.second.get());
|
||||
if (ast->attributes.count(ID::lib_whitebox)) {
|
||||
if (!flag_lib || flag_nowb) {
|
||||
delete ast->attributes.at(ID::lib_whitebox);
|
||||
ast->attributes.erase(ID::lib_whitebox);
|
||||
} else {
|
||||
if (ast->attributes.count(ID::whitebox)) {
|
||||
delete ast->attributes.at(ID::whitebox);
|
||||
ast->attributes.erase(ID::whitebox);
|
||||
}
|
||||
AstNode *n = ast->attributes.at(ID::lib_whitebox);
|
||||
ast->set_attribute(ID::whitebox, n);
|
||||
ast->attributes.erase(ID::lib_whitebox);
|
||||
if (flag_lib && !flag_nowb) {
|
||||
ast->attributes[ID::whitebox] = std::move(
|
||||
ast->attributes[ID::lib_whitebox]
|
||||
);
|
||||
}
|
||||
ast->attributes.erase(ID::lib_whitebox);
|
||||
}
|
||||
for (auto &attr: ast->attributes)
|
||||
log_assert((bool)attr.second.get());
|
||||
|
||||
if (!blackbox_module && ast->attributes.count(ID::blackbox)) {
|
||||
AstNode *n = ast->attributes.at(ID::blackbox);
|
||||
auto& n = ast->attributes.at(ID::blackbox);
|
||||
if (n->type != AST_CONSTANT)
|
||||
ast->input_error("Got blackbox attribute with non-constant value!\n");
|
||||
blackbox_module = n->asBool();
|
||||
}
|
||||
|
||||
if (blackbox_module && ast->attributes.count(ID::whitebox)) {
|
||||
AstNode *n = ast->attributes.at(ID::whitebox);
|
||||
auto& n = ast->attributes.at(ID::whitebox);
|
||||
if (n->type != AST_CONSTANT)
|
||||
ast->input_error("Got whitebox attribute with non-constant value!\n");
|
||||
blackbox_module = !n->asBool();
|
||||
|
|
@ -1200,38 +1214,34 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
|
||||
if (ast->attributes.count(ID::noblackbox)) {
|
||||
if (blackbox_module) {
|
||||
AstNode *n = ast->attributes.at(ID::noblackbox);
|
||||
auto& n = ast->attributes.at(ID::noblackbox);
|
||||
if (n->type != AST_CONSTANT)
|
||||
ast->input_error("Got noblackbox attribute with non-constant value!\n");
|
||||
blackbox_module = !n->asBool();
|
||||
}
|
||||
delete ast->attributes.at(ID::noblackbox);
|
||||
ast->attributes.erase(ID::noblackbox);
|
||||
}
|
||||
|
||||
for (auto &attr: ast->attributes)
|
||||
log_assert((bool)attr.second.get());
|
||||
if (blackbox_module)
|
||||
{
|
||||
if (ast->attributes.count(ID::whitebox)) {
|
||||
delete ast->attributes.at(ID::whitebox);
|
||||
ast->attributes.erase(ID::whitebox);
|
||||
}
|
||||
|
||||
if (ast->attributes.count(ID::lib_whitebox)) {
|
||||
delete ast->attributes.at(ID::lib_whitebox);
|
||||
ast->attributes.erase(ID::lib_whitebox);
|
||||
}
|
||||
|
||||
std::vector<AstNode*> new_children;
|
||||
for (auto child : ast->children) {
|
||||
std::vector<std::unique_ptr<AstNode>> new_children;
|
||||
for (auto& child : ast->children) {
|
||||
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
|
||||
new_children.push_back(child);
|
||||
new_children.push_back(std::move(child));
|
||||
} else if (child->type == AST_PARAMETER) {
|
||||
new_children.push_back(child);
|
||||
new_children.push_back(std::move(child));
|
||||
} else if (child->type == AST_CELL && child->children.size() > 0 && child->children[0]->type == AST_CELLTYPE &&
|
||||
(child->children[0]->str == "$specify2" || child->children[0]->str == "$specify3" || child->children[0]->str == "$specrule")) {
|
||||
new_children.push_back(child);
|
||||
} else {
|
||||
delete child;
|
||||
new_children.push_back(std::move(child));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1245,17 +1255,18 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
ignoreThisSignalsInInitial = RTLIL::SigSpec();
|
||||
|
||||
for (auto &attr : ast->attributes) {
|
||||
log_assert((bool)attr.second.get());
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
module->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
for (size_t i = 0; i < ast->children.size(); i++) {
|
||||
AstNode *node = ast->children[i];
|
||||
const auto& node = ast->children[i];
|
||||
if (node->type == AST_WIRE || node->type == AST_MEMORY)
|
||||
node->genRTLIL();
|
||||
}
|
||||
for (size_t i = 0; i < ast->children.size(); i++) {
|
||||
AstNode *node = ast->children[i];
|
||||
const auto& node = ast->children[i];
|
||||
if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
|
||||
node->genRTLIL();
|
||||
}
|
||||
|
|
@ -1263,7 +1274,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
ignoreThisSignalsInInitial.sort_and_unify();
|
||||
|
||||
for (size_t i = 0; i < ast->children.size(); i++) {
|
||||
AstNode *node = ast->children[i];
|
||||
const auto& node = ast->children[i];
|
||||
if (node->type == AST_INITIAL)
|
||||
node->genRTLIL();
|
||||
}
|
||||
|
|
@ -1277,14 +1288,14 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
continue;
|
||||
module->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
for (const AstNode *node : ast->children)
|
||||
for (const auto& node : ast->children)
|
||||
if (node->type == AST_PARAMETER)
|
||||
current_module->avail_parameters(node->str);
|
||||
}
|
||||
|
||||
if (ast->type == AST_INTERFACE)
|
||||
module->set_bool_attribute(ID::is_interface);
|
||||
module->ast = ast_before_simplify;
|
||||
module->ast = std::move(ast_before_simplify);
|
||||
module->nolatches = flag_nolatches;
|
||||
module->nomeminit = flag_nomeminit;
|
||||
module->nomem2reg = flag_nomem2reg;
|
||||
|
|
@ -1311,8 +1322,8 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
|
|||
RTLIL::Module *
|
||||
AST_INTERNAL::process_and_replace_module(RTLIL::Design *design,
|
||||
RTLIL::Module *old_module,
|
||||
AstNode *new_ast,
|
||||
AstNode *original_ast)
|
||||
AST::AstNode *new_ast,
|
||||
std::unique_ptr<AstNode> original_ast)
|
||||
{
|
||||
// The old module will be deleted. Rename and mark for deletion, using
|
||||
// a static counter to make sure we get a unique name.
|
||||
|
|
@ -1335,7 +1346,7 @@ AST_INTERNAL::process_and_replace_module(RTLIL::Design *design,
|
|||
}
|
||||
|
||||
// Generate RTLIL from AST for the new module and add to the design:
|
||||
RTLIL::Module* new_module = process_module(design, new_ast, false, original_ast);
|
||||
RTLIL::Module* new_module = process_module(design, new_ast, false, std::move(original_ast));
|
||||
|
||||
if (is_top)
|
||||
new_module->set_bool_attribute(ID::top);
|
||||
|
|
@ -1347,17 +1358,17 @@ AST_INTERNAL::process_and_replace_module(RTLIL::Design *design,
|
|||
static void rename_in_package_stmts(AstNode *pkg)
|
||||
{
|
||||
std::unordered_set<std::string> idents;
|
||||
for (AstNode *item : pkg->children)
|
||||
for (auto& item : pkg->children)
|
||||
idents.insert(item->str);
|
||||
std::function<void(AstNode*)> rename =
|
||||
[&rename, &idents, pkg](AstNode *node) {
|
||||
for (AstNode *child : node->children) {
|
||||
std::function<void(std::unique_ptr<AstNode>&)> rename =
|
||||
[&rename, &idents, pkg](std::unique_ptr<AstNode>& node) {
|
||||
for (auto& child : node->children) {
|
||||
if (idents.count(child->str))
|
||||
child->str = pkg->str + "::" + child->str.substr(1);
|
||||
rename(child);
|
||||
}
|
||||
};
|
||||
for (AstNode *item : pkg->children)
|
||||
for (auto& item : pkg->children)
|
||||
if (item->type == AST_FUNCTION || item->type == AST_TASK)
|
||||
rename(item);
|
||||
}
|
||||
|
|
@ -1390,17 +1401,17 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
ast->fixup_hierarchy_flags(true);
|
||||
|
||||
log_assert(current_ast->type == AST_DESIGN);
|
||||
for (AstNode *child : current_ast->children)
|
||||
for (const auto& child : current_ast->children)
|
||||
{
|
||||
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
|
||||
{
|
||||
for (auto n : design->verilog_globals)
|
||||
for (auto& n : design->verilog_globals)
|
||||
child->children.push_back(n->clone());
|
||||
|
||||
// append nodes from previous packages using package-qualified names
|
||||
for (auto &n : design->verilog_packages) {
|
||||
for (auto& n : design->verilog_packages) {
|
||||
for (auto &o : n->children) {
|
||||
AstNode *cloned_node = o->clone();
|
||||
auto cloned_node = o->clone();
|
||||
// log("cloned node %s\n", type2str(cloned_node->type).c_str());
|
||||
if (cloned_node->type == AST_ENUM) {
|
||||
for (auto &e : cloned_node->children) {
|
||||
|
|
@ -1410,7 +1421,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
} else {
|
||||
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
|
||||
}
|
||||
child->children.push_back(cloned_node);
|
||||
child->children.push_back(std::move(cloned_node));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1419,7 +1430,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
|
||||
bool defer_local = defer;
|
||||
if (!defer_local)
|
||||
for (const AstNode *node : child->children)
|
||||
for (const auto& node : child->children)
|
||||
if (node->type == AST_PARAMETER && param_has_no_default(node))
|
||||
{
|
||||
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str());
|
||||
|
|
@ -1447,13 +1458,13 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
}
|
||||
}
|
||||
|
||||
process_module(design, child, defer_local);
|
||||
process_module(design, child.get(), defer_local);
|
||||
current_ast_mod = nullptr;
|
||||
}
|
||||
else if (child->type == AST_PACKAGE) {
|
||||
// process enum/other declarations
|
||||
child->simplify(true, 1, -1, false);
|
||||
rename_in_package_stmts(child);
|
||||
rename_in_package_stmts(child.get());
|
||||
design->verilog_packages.push_back(child->clone());
|
||||
current_scope.clear();
|
||||
}
|
||||
|
|
@ -1470,16 +1481,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
|
|||
current_scope.clear();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// AstModule destructor
|
||||
AstModule::~AstModule()
|
||||
{
|
||||
if (ast != NULL)
|
||||
delete ast;
|
||||
}
|
||||
|
||||
|
||||
// An interface port with modport is specified like this:
|
||||
// <interface_name>.<modport_name>
|
||||
// This function splits the interface_name from the modport_name, and fails if it is not a valid combination
|
||||
|
|
@ -1516,7 +1520,7 @@ AstNode * AST::find_modport(AstNode *intf, std::string name)
|
|||
for (auto &ch : intf->children)
|
||||
if (ch->type == AST_MODPORT)
|
||||
if (ch->str == name) // Modport found
|
||||
return ch;
|
||||
return ch.get();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -1524,7 +1528,7 @@ AstNode * AST::find_modport(AstNode *intf, std::string name)
|
|||
void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport)
|
||||
{
|
||||
for (auto w : intfmodule->wires()){
|
||||
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
|
||||
auto wire = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
|
||||
std::string origname = log_id(w->name);
|
||||
std::string newname = intfname + "." + origname;
|
||||
wire->str = newname;
|
||||
|
|
@ -1543,16 +1547,13 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
|
|||
}
|
||||
}
|
||||
if (found_in_modport) {
|
||||
module_ast->children.push_back(wire);
|
||||
}
|
||||
else { // If not found in modport, do not create port
|
||||
delete wire;
|
||||
module_ast->children.push_back(std::move(wire));
|
||||
}
|
||||
}
|
||||
else { // If no modport, set inout
|
||||
wire->is_input = true;
|
||||
wire->is_output = true;
|
||||
module_ast->children.push_back(wire);
|
||||
module_ast->children.push_back(std::move(wire));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1570,7 +1571,7 @@ bool AstModule::reprocess_if_necessary(RTLIL::Design *design)
|
|||
log("Reprocessing module %s because instantiated module %s has become available.\n",
|
||||
log_id(name), log_id(modname));
|
||||
loadconfig();
|
||||
process_and_replace_module(design, this, ast, NULL);
|
||||
process_and_replace_module(design, this, ast.get(), NULL);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
|
@ -1583,32 +1584,32 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
{
|
||||
loadconfig();
|
||||
|
||||
AstNode *new_ast = ast->clone();
|
||||
auto new_ast = ast->clone();
|
||||
for (auto &intf : local_interfaces) {
|
||||
std::string intfname = intf.first.str();
|
||||
RTLIL::Module *intfmodule = intf.second;
|
||||
for (auto w : intfmodule->wires()){
|
||||
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
|
||||
auto wire = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
|
||||
std::string newname = log_id(w->name);
|
||||
newname = intfname + "." + newname;
|
||||
wire->str = newname;
|
||||
new_ast->children.push_back(wire);
|
||||
new_ast->children.push_back(std::move(wire));
|
||||
}
|
||||
}
|
||||
|
||||
AstNode *ast_before_replacing_interface_ports = new_ast->clone();
|
||||
auto ast_before_replacing_interface_ports = new_ast->clone();
|
||||
|
||||
// Explode all interface ports. Note this will only have an effect on 'top
|
||||
// level' modules. Other sub-modules will have their interface ports
|
||||
// exploded via the derive(..) function
|
||||
for (size_t i =0; i<new_ast->children.size(); i++)
|
||||
{
|
||||
AstNode *ch2 = new_ast->children[i];
|
||||
const auto& ch2 = new_ast->children[i];
|
||||
if (ch2->type == AST_INTERFACEPORT) { // Is an interface port
|
||||
std::string name_port = ch2->str; // Name of the interface port
|
||||
if (ch2->children.size() > 0) {
|
||||
for(size_t j=0; j<ch2->children.size();j++) {
|
||||
AstNode *ch = ch2->children[j];
|
||||
const auto& ch = ch2->children[j];
|
||||
if(ch->type == AST_INTERFACEPORTTYPE) { // Found the AST node containing the type of the interface
|
||||
std::pair<std::string,std::string> res = split_modport_from_type(ch->str);
|
||||
std::string interface_type = res.first;
|
||||
|
|
@ -1616,11 +1617,11 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
if (design->module(interface_type) != nullptr) {
|
||||
// Add a cell to the module corresponding to the interface port such that
|
||||
// it can further propagated down if needed:
|
||||
AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE);
|
||||
auto celltype_for_intf = std::make_unique<AstNode>(AST_CELLTYPE);
|
||||
celltype_for_intf->str = interface_type;
|
||||
AstNode *cell_for_intf = new AstNode(AST_CELL, celltype_for_intf);
|
||||
auto cell_for_intf = std::make_unique<AstNode>(AST_CELL, std::move(celltype_for_intf));
|
||||
cell_for_intf->str = name_port + "_inst_from_top_dummy";
|
||||
new_ast->children.push_back(cell_for_intf);
|
||||
new_ast->children.push_back(std::move(cell_for_intf));
|
||||
|
||||
// Get all members of this non-overridden dummy interface instance:
|
||||
RTLIL::Module *intfmodule = design->module(interface_type); // All interfaces should at this point in time (assuming
|
||||
|
|
@ -1628,9 +1629,9 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
// present in design->modules_
|
||||
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
|
||||
std::string interface_modport_compare_str = "\\" + interface_modport;
|
||||
AstNode *modport = find_modport(ast_module_of_interface->ast, interface_modport_compare_str); // modport == NULL if no modport
|
||||
AstNode *modport = find_modport(ast_module_of_interface->ast.get(), interface_modport_compare_str); // modport == NULL if no modport
|
||||
// Iterate over all wires in the interface and add them to the module:
|
||||
explode_interface_port(new_ast, intfmodule, name_port, modport);
|
||||
explode_interface_port(new_ast.get(), intfmodule, name_port, modport);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -1642,9 +1643,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
// Generate RTLIL from AST for the new module and add to the design,
|
||||
// renaming this module to move it out of the way.
|
||||
RTLIL::Module* new_module =
|
||||
process_and_replace_module(design, this, new_ast, ast_before_replacing_interface_ports);
|
||||
|
||||
delete new_ast;
|
||||
process_and_replace_module(design, this, new_ast.get(), std::move(ast_before_replacing_interface_ports));
|
||||
|
||||
// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
|
||||
new_module->set_bool_attribute(ID::interfaces_replaced_in_module);
|
||||
|
|
@ -1654,7 +1653,7 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
// This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
|
||||
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool /*mayfail*/)
|
||||
{
|
||||
AstNode *new_ast = NULL;
|
||||
std::unique_ptr<AstNode> new_ast = NULL;
|
||||
std::string modname = derive_common(design, parameters, &new_ast);
|
||||
|
||||
// Since interfaces themselves may be instantiated with different parameters,
|
||||
|
|
@ -1690,14 +1689,14 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
if (modports.count(intfname) > 0) {
|
||||
std::string interface_modport = modports.at(intfname).str();
|
||||
AstModule *ast_module_of_interface = (AstModule*)intfmodule;
|
||||
AstNode *ast_node_of_interface = ast_module_of_interface->ast;
|
||||
AstNode *ast_node_of_interface = ast_module_of_interface->ast.get();
|
||||
modport = find_modport(ast_node_of_interface, interface_modport);
|
||||
}
|
||||
// Iterate over all wires in the interface and add them to the module:
|
||||
explode_interface_port(new_ast, intfmodule, intfname, modport);
|
||||
explode_interface_port(new_ast.get(), intfmodule, intfname, modport);
|
||||
}
|
||||
|
||||
process_module(design, new_ast, false);
|
||||
process_module(design, new_ast.get(), false);
|
||||
design->module(modname)->check();
|
||||
|
||||
RTLIL::Module* mod = design->module(modname);
|
||||
|
|
@ -1734,7 +1733,6 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
|
||||
}
|
||||
|
||||
delete new_ast;
|
||||
return modname;
|
||||
}
|
||||
|
||||
|
|
@ -1743,18 +1741,17 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
|
|||
{
|
||||
bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
|
||||
|
||||
AstNode *new_ast = NULL;
|
||||
std::unique_ptr<AstNode> new_ast = NULL;
|
||||
std::string modname = derive_common(design, parameters, &new_ast, quiet);
|
||||
|
||||
if (!design->has(modname) && new_ast) {
|
||||
new_ast->str = modname;
|
||||
process_module(design, new_ast, false, NULL, quiet);
|
||||
process_module(design, new_ast.get(), false, NULL, quiet);
|
||||
design->module(modname)->check();
|
||||
} else if (!quiet) {
|
||||
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
|
||||
}
|
||||
|
||||
delete new_ast;
|
||||
return modname;
|
||||
}
|
||||
|
||||
|
|
@ -1784,7 +1781,7 @@ std::string AST::derived_module_name(std::string stripped_name, const std::vecto
|
|||
}
|
||||
|
||||
// create a new parametric module (when needed) and return the name of the generated module
|
||||
std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet)
|
||||
std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, std::unique_ptr<AstNode>* new_ast_out, bool quiet)
|
||||
{
|
||||
std::string stripped_name = name.str();
|
||||
(*new_ast_out) = nullptr;
|
||||
|
|
@ -1794,7 +1791,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
|
||||
int para_counter = 0;
|
||||
std::vector<std::pair<RTLIL::IdString, RTLIL::Const>> named_parameters;
|
||||
for (const auto child : ast->children) {
|
||||
for (const auto& child : ast->children) {
|
||||
if (child->type != AST_PARAMETER)
|
||||
continue;
|
||||
para_counter++;
|
||||
|
|
@ -1828,12 +1825,12 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
pool<IdString> rewritten;
|
||||
rewritten.reserve(GetSize(parameters));
|
||||
|
||||
AstNode *new_ast = ast->clone();
|
||||
auto new_ast = ast->clone();
|
||||
if (!new_ast->attributes.count(ID::hdlname))
|
||||
new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name.substr(1)));
|
||||
|
||||
para_counter = 0;
|
||||
for (auto child : new_ast->children) {
|
||||
for (auto& child : new_ast->children) {
|
||||
if (child->type != AST_PARAMETER)
|
||||
continue;
|
||||
para_counter++;
|
||||
|
|
@ -1853,9 +1850,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
rewrite_parameter:
|
||||
if (param_has_no_default(child))
|
||||
child->children.insert(child->children.begin(), nullptr);
|
||||
delete child->children.at(0);
|
||||
if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {
|
||||
child->children[0] = new AstNode(AST_REALVALUE);
|
||||
child->children[0] = std::make_unique<AstNode>(AST_REALVALUE);
|
||||
child->children[0]->realvalue = std::stod(it->second.decode_string());
|
||||
} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
||||
child->children[0] = AstNode::mkconst_str(it->second.decode_string());
|
||||
|
|
@ -1868,17 +1864,17 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
|
|||
for (const auto ¶m : parameters) {
|
||||
if (rewritten.count(param.first))
|
||||
continue;
|
||||
AstNode *defparam = new AstNode(AST_DEFPARAM, new AstNode(AST_IDENTIFIER));
|
||||
auto defparam = std::make_unique<AstNode>(AST_DEFPARAM, std::make_unique<AstNode>(AST_IDENTIFIER));
|
||||
defparam->children[0]->str = param.first.str();
|
||||
if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
|
||||
defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string()));
|
||||
else
|
||||
defparam->children.push_back(AstNode::mkconst_bits(param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
|
||||
new_ast->children.push_back(defparam);
|
||||
new_ast->children.push_back(std::move(defparam));
|
||||
}
|
||||
|
||||
new_ast->fixup_hierarchy_flags(true);
|
||||
(*new_ast_out) = new_ast;
|
||||
new_ast_out->reset(new_ast.release());
|
||||
return modname;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue