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update test to use suggested selection for assertions
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3 changed files with 12 additions and 3 deletions
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@ -38,6 +38,7 @@ DA:48,0
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DA:49,0
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DA:49,0
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DA:52,1
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DA:52,1
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DA:53,0
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DA:53,0
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LF:39
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DA:56,1
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LF:40
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LH:24
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LH:24
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end_of_record
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end_of_record
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@ -52,4 +52,8 @@ module top (
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assign out1 = cone1_3 | (reg1 ^ 8'hA5);
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assign out1 = cone1_3 | (reg1 ^ 8'hA5);
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assign out2 = cone2_3 & (reg3 | 8'h5A);
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assign out2 = cone2_3 & (reg3 | 8'h5A);
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always @(posedge clk) begin
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assert (out1 == 8'h42);
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end
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endmodule
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endmodule
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@ -1,4 +1,8 @@
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read_verilog lcov.v
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read_verilog -formal lcov.v
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prep -top top
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prep -top top
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linecoverage -lcov lcov.out o:\out1 %ci*
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async2sync
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chformal -lower
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select -set covered t:$assert %ci*
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select -set irrelevant o:* %ci* %n
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linecoverage -lcov lcov.out @covered @irrelevant %u
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exec -expect-return 0 -- diff -q lcov.out lcov.gold
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exec -expect-return 0 -- diff -q lcov.out lcov.gold
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