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update test to use suggested selection for assertions
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3 changed files with 12 additions and 3 deletions
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@ -52,4 +52,8 @@ module top (
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assign out1 = cone1_3 | (reg1 ^ 8'hA5);
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assign out2 = cone2_3 & (reg3 | 8'h5A);
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always @(posedge clk) begin
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assert (out1 == 8'h42);
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end
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endmodule
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