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Added additional functionality and cleanups in sigtools.h and celltypes.h

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This commit is contained in:
Clifford Wolf 2013-03-15 10:22:23 +01:00
parent 3377a04bf2
commit 89f009d171
2 changed files with 33 additions and 0 deletions
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9
kernel/celltypes.h
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@ -29,6 +29,15 @@ struct CellTypes
std::set<std::string> cell_types; std::set<std::string> cell_types;
std::vector<const RTLIL::Design*> designs; std::vector<const RTLIL::Design*> designs;
CellTypes()
{
}
CellTypes(const RTLIL::Design *design)
{
setup(design);
}
void setup(const RTLIL::Design *design = NULL) void setup(const RTLIL::Design *design = NULL)
{ {
if (design) if (design)

24
kernel/sigtools.h
View file

@ -164,6 +164,18 @@ struct SigSet
} }
} }
void insert(RTLIL::SigSpec sig, const std::set<T> &data)
{
sig.expand();
for (auto &c : sig.chunks) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
bitDef_t bit(c.wire, c.offset);
bits[bit].insert(data.begin(), data.end());
}
}
void erase(RTLIL::SigSpec sig) void erase(RTLIL::SigSpec sig)
{ {
sig.expand(); sig.expand();
@ -188,6 +200,18 @@ struct SigSet
} }
} }
void erase(RTLIL::SigSpec sig, const std::set<T> &data)
{
sig.expand();
for (auto &c : sig.chunks) {
if (c.wire == NULL)
continue;
assert(c.width == 1);
bitDef_t bit(c.wire, c.offset);
bits[bit].erase(data.begin(), data.end());
}
}
void find(RTLIL::SigSpec sig, std::set<T> &result) void find(RTLIL::SigSpec sig, std::set<T> &result)
{ {
sig.expand(); sig.expand();