mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 10:55:51 +00:00
Code Activity

Add "read_verilog -noassert -noassume -assert-assumes"

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-09-24 20:51:16 +02:00 • committed by Jim Lawson
parent e8431d1508
commit 89ef6600bc
3 changed files with 49 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

9
frontends/verilog/verilog_frontend.h
View file

@ -54,12 +54,21 @@ namespace VERILOG_FRONTEND
// running in -formal mode
extern bool formal_mode;
// running in -noassert mode
extern bool noassert_mode;
// running in -noassume mode
extern bool noassume_mode;
// running in -norestrict mode
extern bool norestrict_mode;
// running in -assume-asserts mode
extern bool assume_asserts_mode;
// running in -assert-assumes mode
extern bool assert_assumes_mode;
// running in -lib mode
extern bool lib_mode;