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Add "read_verilog -noassert -noassume -assert-assumes"

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-09-24 20:51:16 +02:00 • committed by Jim Lawson
parent e8431d1508
commit 89ef6600bc
3 changed files with 49 additions and 6 deletions
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23
frontends/verilog/verilog_frontend.cc
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@ -66,12 +66,21 @@ struct VerilogFrontend : public Frontend {
log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
log("\n");
log(" -noassert\n");
log(" ignore assert() statements\n");
log("\n");
log(" -noassume\n");
log(" ignore assume() statements\n");
log("\n");
log(" -norestrict\n");
log(" ignore restrict() assertions\n");
log(" ignore restrict() statements\n");
log("\n");
log(" -assume-asserts\n");
log(" treat all assert() statements like assume() statements\n");
log("\n");
log(" -assert-assumes\n");
log(" treat all assume() statements like assert() statements\n");
log("\n");
log(" -dump_ast1\n");
log(" dump abstract syntax tree (before simplification)\n");
log("\n");
@ -229,6 +238,14 @@ struct VerilogFrontend : public Frontend {
formal_mode = true;
continue;
}
if (arg == "-noassert") {
noassert_mode = true;
continue;
}
if (arg == "-noassume") {
noassume_mode = true;
continue;
}
if (arg == "-norestrict") {
norestrict_mode = true;
continue;
@ -237,6 +254,10 @@ struct VerilogFrontend : public Frontend {
assume_asserts_mode = true;
continue;
}
if (arg == "-assert-assumes") {
assert_assumes_mode = true;
continue;
}
if (arg == "-dump_ast1") {
flag_dump_ast1 = true;
continue;