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Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup

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xaiger: do not derive cells
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Eddie Hung 2020-05-24 10:10:50 -07:00 committed by GitHub
parent 227c3ff310 33b03ce904
commit 89ed34fe55
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2 changed files with 14 additions and 7 deletions
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8
backends/aiger/xaiger.cc
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@ -248,6 +248,7 @@ struct XAigerWriter
auto it = cell->attributes.find(ID::abc9_box_seq); auto it = cell->attributes.find(ID::abc9_box_seq);
if (it != cell->attributes.end()) { if (it != cell->attributes.end()) {
log_assert(!cell->has_keep_attr()); log_assert(!cell->has_keep_attr());
log_assert(cell->parameters.empty());
int abc9_box_seq = it->second.as_int(); int abc9_box_seq = it->second.as_int();
if (GetSize(box_list) <= abc9_box_seq) if (GetSize(box_list) <= abc9_box_seq)
box_list.resize(abc9_box_seq+1); box_list.resize(abc9_box_seq+1);
@ -260,13 +261,6 @@ struct XAigerWriter
continue; continue;
} }
if (!cell->parameters.empty()) {
auto derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
log_assert(inst_module);
log_assert(inst_module->get_blackbox_attribute());
}
if (!timing.count(inst_module->name)) if (!timing.count(inst_module->name))
timing.setup_module(inst_module); timing.setup_module(inst_module);
auto &t = timing.at(inst_module->name).arrival; auto &t = timing.at(inst_module->name).arrival;

13
tests/various/xaiger.ys Normal file
View file

@ -0,0 +1,13 @@
read_verilog <<EOT
module top(input a, b, output c);
bb #(1) bb();
endmodule
module bb(input a, b, output c);
parameter p = 0;
assign c = a ^ b;
endmodule
EOT
blackbox bb
hierarchy
write_xaiger /dev/null