From 89d56882bac06cbb733da0c67d05e639904179a5 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 15 Apr 2026 12:37:18 -0700 Subject: [PATCH] Pullup/pulldown primitives --- frontends/verific/verific.cc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 375c4821d..25f5928ff 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -753,6 +753,16 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr return true; } + if (inst->Type() == PRIM_PULLUP) { + module->connect(net_map_at(inst->GetOutput()), RTLIL::State::S1); + return true; + } + + if (inst->Type() == PRIM_PULLDOWN) { + module->connect(net_map_at(inst->GetOutput()), RTLIL::State::S0); + return true; + } + if (inst->Type() == PRIM_MUX) { module->addMuxGate(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput())); return true; @@ -889,6 +899,16 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr return true; } + if (inst->Type() == PRIM_PULLUP) { + module->connect(net_map_at(inst->GetOutput()), RTLIL::State::S1); + return true; + } + + if (inst->Type() == PRIM_PULLDOWN) { + module->connect(net_map_at(inst->GetOutput()), RTLIL::State::S0); + return true; + } + if (inst->Type() == PRIM_MUX) { cell = module->addMux(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput())); import_attributes(cell->attributes, inst);