diff --git a/Makefile b/Makefile
index d8d7f5a9a..cc573c06e 100644
--- a/Makefile
+++ b/Makefile
@@ -147,7 +147,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.43+22
+YOSYS_VER := 0.43+34
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
index db34f041b..03a1faefa 100644
--- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst
+++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
@@ -115,7 +115,7 @@ leads us to the third diagram:
    
    Output of the third :cmd:ref:`show` command in :ref:`example_ys`
    
-Here we see that the :cmd:ref:`proc` command not only has removed the artifacts
+Here we see that the :cmd:ref:`opt` command not only has removed the artifacts
 left behind by :cmd:ref:`proc`, but also determined correctly that it can remove
 the first ``$mux`` cell without changing the behavior of the circuit.
 
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index e23f13152..70e54dbd0 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1129,31 +1129,40 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
 		design = yosys_design;
 
 	if (command == "auto") {
-		std::string filename_trim = filename;
-		if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".gz") == 0)
-			filename_trim.erase(filename_trim.size()-3);
-		if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-2, std::string::npos, ".v") == 0)
-			command = " -vlog2k";
-		else if (filename_trim.size() > 2 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".sv") == 0)
-			command = " -sv";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vhd") == 0)
-			command = " -vhdl";
-		else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".blif") == 0)
-			command = "blif";
-		else if (filename_trim.size() > 5 && filename_trim.compare(filename_trim.size()-6, std::string::npos, ".eblif") == 0)
-			command = "blif";
-		else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0)
-			command = "json";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0)
-			command = "rtlil";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0)
-			command = "script";
-		else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0)
-			command = "tcl";
-		else if (filename == "-")
-			command = "script";
-		else
-			log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
+	  std::string filename_trim = filename;
+	  
+	  auto has_extension = [](const std::string& filename, const std::string& extension) {
+	    if (filename.size() >= extension.size()) {
+	      return filename.compare(filename.size() - extension.size(), extension.size(), extension) == 0;
+	    }
+	    return false;
+	  };
+
+	  if (has_extension(filename_trim, ".gz")) {
+	    filename_trim.erase(filename_trim.size() - 3);
+	  }
+	  
+	  if (has_extension(filename_trim, ".v")) {
+	    command = " -vlog2k";
+	  } else if (has_extension(filename_trim, ".sv")) {
+	    command = " -sv";
+	  } else if (has_extension(filename_trim, ".vhd") || has_extension(filename_trim, ".vhdl")) {
+	    command = " -vhdl";
+	  } else if (has_extension(filename_trim, ".blif") || has_extension(filename_trim, ".eblif")) {
+	    command = "blif";
+	  } else if (has_extension(filename_trim, ".json")) {
+	    command = "json";
+	  } else if (has_extension(filename_trim, ".il")) {
+	    command = "rtlil";
+	  } else if (has_extension(filename_trim, ".ys")) {
+	    command = "script";
+	  } else if (has_extension(filename_trim, ".tcl")) {
+	    command = "tcl";
+	  } else if (filename == "-") {
+	    command = "script";
+	  } else {
+	    log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
+	  }
 	}
 
 	if (command == "script")
diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc
index ebc2377aa..ae6774547 100644
--- a/passes/proc/proc_rom.cc
+++ b/passes/proc/proc_rom.cc
@@ -183,6 +183,12 @@ struct RomWorker
 		mem.rd_ports.push_back(std::move(rd));
 
 		mem.emit();
+
+		if (sw->has_attribute(ID::src)) {
+			mem.inits[0].cell->attributes[ID::src] = sw->attributes[ID::src];
+			mem.rd_ports[0].cell->attributes[ID::src] = sw->attributes[ID::src];
+		}
+
 		for (auto cs: sw->cases)
 			delete cs;
 		sw->cases.clear();
diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc
index 25416b6c4..5553abec2 100644
--- a/passes/sat/synthprop.cc
+++ b/passes/sat/synthprop.cc
@@ -185,35 +185,25 @@ struct SyntProperties : public Pass {
 		log("\n");
 		log("    synthprop [options]\n");
 		log("\n");
-		log("This creates synthesizable properties for selected module.\n");
+		log("This creates synthesizable properties for the selected module.\n");
 		log("\n");
 		log("\n");
 		log("    -name <portname>\n");
-		log("\n");
-		log("Name output port for assertions (default: assertions).\n");
-		log("\n");
+		log("        name of the output port for assertions (default: assertions).\n");
 		log("\n");
 		log("    -map <filename>\n");
-		log("\n");
-		log("Write port mapping for synthesizable properties.\n");
-		log("\n");
+		log("        write the port mapping for synthesizable properties into the given file.\n");
 		log("\n");
 		log("    -or_outputs\n");
-		log("\n");
-		log("Or all outputs together to create a single output that goes high when any\n");
-		log("property is violated, instead of generating individual output bits.\n");
-		log("\n");
+		log("        Or all outputs together to create a single output that goes high when\n");
+		log("        any property is violated, instead of generating individual output bits.\n");
 		log("\n");
 		log("    -reset <portname>\n");
-		log("\n");
-		log("Name of top-level reset input. Latch a high state on the generated outputs\n");
-		log("until an asynchronous top-level reset input is activated.\n");
-		log("\n");
+		log("        name of the top-level reset input. Latch a high state on the generated\n");
+		log("        outputs until an asynchronous top-level reset input is activated.\n");
 		log("\n");
 		log("    -resetn <portname>\n");
-		log("\n");
-		log("Name of top-level reset input (inverse polarity). Latch a high state on the\n");
-		log("generated outputs until an asynchronous top-level reset input is activated.\n");
+		log("        like above but with inverse polarity\n");
 		log("\n");
 		log("\n");
 	}