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Removed $bu0 cell type
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parent
b9cb483f3e
commit
8927aa6148
18 changed files with 27 additions and 103 deletions
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@ -181,7 +181,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
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log("\n");
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}
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cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str());
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cover_list("opt.opt_const.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
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module->remove(cell);
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did_something = true;
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@ -236,7 +236,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (do_fine)
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{
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if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" ||
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if (cell->type == "$not" || cell->type == "$pos" ||
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cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
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if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map))
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goto next_cell;
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@ -586,7 +586,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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if (!keepdc)
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{
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bool identity_bu0 = false;
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bool identity_wrt_a = false;
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bool identity_wrt_b = false;
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@ -607,7 +606,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
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if (b.is_fully_const() && b.as_bool() == false)
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identity_wrt_a = true, identity_bu0 = true;
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identity_wrt_a = true;
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}
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if (cell->type == "$mul")
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@ -646,7 +645,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
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}
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cell->type = identity_bu0 ? "$bu0" : "$pos";
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cell->type = "$pos";
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cell->unsetPort("\\B");
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cell->parameters.erase("\\B_WIDTH");
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cell->parameters.erase("\\B_SIGNED");
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@ -840,7 +839,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
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FOLD_2ARG_CELL(pow)
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FOLD_1ARG_CELL(pos)
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FOLD_1ARG_CELL(bu0)
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FOLD_1ARG_CELL(neg)
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// be very conservative with optimizing $mux cells as we do not want to break mux trees
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