Removed $bu0 cell type

manual/CHAPTER_CellLib.tex

@@ -97,12 +97,6 @@ The width of the output port \B{Y}.
 
 Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
 
-The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always
-extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments
-with {\tt x}-bits if the most significant bit is {\tt x}.) This is used
-internally to correctly implement the {\tt ==} and {\tt !=} operators for
-constant arguments.
-
 \subsection{Multiplexers}
 
 Multiplexers are generated by the Verilog HDL frontend for {\tt

manual/PRESENTATION_Prog.tex

@@ -300,7 +300,7 @@ The {\tt type} may refer to another module in the same design, a cell name from
 cell name from the internal cell library:
 
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
-$not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
+$not $pos $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
 $reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
 $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
 $dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_

manual/command-reference-manual.tex

@@ -1204,7 +1204,7 @@ unless another prefix is specified using -prefix <prefix>.
 This pass maps a small selection of simple coarse-grain cells to yosys gate
 primitives. The following internal cell types are mapped by this pass:
 
-  $not, $pos, $bu0, $and, $or, $xor, $xnor
+  $not, $pos, $and, $or, $xor, $xnor
   $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
   $logic_not, $logic_and, $logic_or, $mux
   $sr, $dff, $dffsr, $adff, $dlatch