mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Removed $bu0 cell type

Browse source
This commit is contained in:
Clifford Wolf 2014-09-04 02:07:52 +02:00
parent b9cb483f3e
commit 8927aa6148
18 changed files with 27 additions and 103 deletions
Download patch file Download diff file Expand all files Collapse all files

21
kernel/calc.cc
View file

@ -26,19 +26,6 @@
YOSYS_NAMESPACE_BEGIN
static void extend(RTLIL::Const &arg, int width, bool is_signed)
{
RTLIL::State padding = RTLIL::State::S0;
if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1))
padding = arg.bits.back();
while (int(arg.bits.size()) < width)
arg.bits.push_back(padding);
arg.bits.resize(width);
}
static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
{
RTLIL::State padding = RTLIL::State::S0;
@ -580,14 +567,6 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo
return arg1_ext;
}
RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
extend_u0(arg1_ext, result_len, signed1);
return arg1_ext;
}
RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;