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SystemVerilog support for implicit named port connections

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This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
This commit is contained in:
tux3 2019-06-05 00:47:54 +02:00
parent 1332051f33
commit 88f5977093
5 changed files with 59 additions and 12 deletions
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15
tests/tools/autotest.sh
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@ -89,6 +89,13 @@ done
compile_and_run() {
exe="$1"; output="$2"; shift 2
ext=${1##*.}
if [ "$ext" == "sv" ]; then
language_gen="-g2012"
else
language_gen="-g2005"
fi
if $use_modelsim; then
altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
/opt/altera/$altver/modelsim_ase/bin/vlib work
@ -99,7 +106,7 @@ compile_and_run() {
/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
else
iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
vvp -n "$exe"
fi
}
@ -110,7 +117,7 @@ for fn
do
bn=${fn%.*}
ext=${fn##*.}
if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
echo "Invalid argument: $fn" >&2
exit 1
fi
@ -123,6 +130,10 @@ do
echo -n "Test: $bn "
fi
if [ "$ext" == sv ]; then
frontend="$frontend -sv"
fi
rm -f ${bn}.{err,log,skip}
mkdir -p ${bn}.out
rm -rf ${bn}.out/*