mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Be more conservative with printing decimal numbers in verilog backend

Browse source
This commit is contained in:
Clifford Wolf 2014-08-02 21:54:02 +02:00
parent ca1b5d50e0
commit 88cf00ce78
1 changed files with 3 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

5
backends/verilog/verilog_backend.cc
View file

@ -163,11 +163,12 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
log_assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
goto dump_bits;
if (data.bits[i] == RTLIL::S1 && (i - offset) == 31)
goto dump_bits;
if (data.bits[i] == RTLIL::S1)
val |= 1 << (i - offset);
}
// fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val));
fprintf(f, "%d", val);
fprintf(f, "32'%sd%d", set_signed ? "s" : "", val);
} else {
dump_bits:
fprintf(f, "%d'%sb", width, set_signed ? "s" : "");