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Oopsy!

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This commit is contained in:
Alain Dargelas 2024-11-16 17:04:07 -08:00
parent dd7ad14096
commit 88c847f733
1 changed files with 1 additions and 1 deletions
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2
backends/verilog/verilog_backend.cc
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@ -2359,7 +2359,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
wires[wire->port_id] = wire; wires[wire->port_id] = wire;
} }
for (int port_id = 1; port_id < max_port_id; port_id++) { for (int port_id = 1; port_id <= max_port_id; port_id++) {
Wire *wire = wires[port_id]; Wire *wire = wires[port_id];
if (wire) { if (wire) {
if (port_id != 1) if (port_id != 1)