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Docs: Verific but with sentences
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@ -15,18 +15,17 @@ form, you may be able to compile Yosys with partial Verific support yourself.
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The Yosys-Verific patch
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The Yosys-Verific patch
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-----------------------
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-----------------------
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* To provide the best integration between Yosys and Verific, some features are
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YosysHQ maintains and develops a patch for Verific in order to better integrate
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required to be patched into the Verific library.
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with Yosys and to provide features required by some of the formal verification
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* Synthesis from RTL may be possible without this patch, however we are unable
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front-end tools. Synthesis from RTL may be possible without this patch, however
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to provide support for any Yosys+Verific builds without it.
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we are unable to provide support for any Yosys+Verific builds without it. To
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* Needed for some of the formal verification front-end tools
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license this patch for your own Yosys builds, `contact YosysHQ`_.
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* `contact YosysHQ`_ about licensing this patch for your own Yosys builds.
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.. warning::
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.. warning::
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Some of the formal verification front-end tools may not be fully supported
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Some of the formal verification front-end tools may not be fully supported
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without the full TabbyCAD suite. If you are wanting to use these tools, make
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without the full TabbyCAD suite. If you are wanting to use these tools,
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sure to `contact YosysHQ`_ and ask us if the Yosys-Verific patch is right for
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including SBY, make sure to ask us if the Yosys-Verific patch is right for
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you.
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you.
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Compile options
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Compile options
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@ -93,6 +92,10 @@ Yosys builds:
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Partially supported builds
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Partially supported builds
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. todo:: still unclear on the purpose of this section.
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Are these the configurations we have tested as being able to compile?
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To be able to compile Yosys with Verific, the Verific library must have support
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To be able to compile Yosys with Verific, the Verific library must have support
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for at least one HDL language with RTL elaboration enabled. The following table
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for at least one HDL language with RTL elaboration enabled. The following table
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lists a series of build configurations which are possible, but only provide a
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lists a series of build configurations which are possible, but only provide a
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