mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-14 04:48:46 +00:00
Mostly coding style related fixes in rmports pass
This commit is contained in:
parent
9fe6bc48a9
commit
88983f5012
|
@ -32,19 +32,22 @@ struct RmportsPassPass : public Pass {
|
||||||
{
|
{
|
||||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" rmports\n");
|
log(" rmports [selection]\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log("This pass identifies ports in the top-level design which are not used or driven\n");
|
log("This pass identifies ports in the selected modules which are not used or\n");
|
||||||
log("and removes them\n");
|
log("driven and removes them.\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual void execute(std::vector<std::string> /*args*/, RTLIL::Design *design)
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
||||||
{
|
{
|
||||||
log_header(design, "Executing RMPORTS pass (remove top level ports with no connections).\n");
|
log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
|
||||||
|
|
||||||
|
size_t argidx = 1;
|
||||||
|
extra_args(args, argidx, design);
|
||||||
|
|
||||||
// The set of ports we removed
|
// The set of ports we removed
|
||||||
std::map< RTLIL::IdString, std::set<RTLIL::IdString> > removed_ports;
|
dict<IdString, pool<IdString>> removed_ports;
|
||||||
|
|
||||||
// Find all of the unused ports, and remove them from that module
|
// Find all of the unused ports, and remove them from that module
|
||||||
auto modules = design->selected_modules();
|
auto modules = design->selected_modules();
|
||||||
|
@ -56,7 +59,7 @@ struct RmportsPassPass : public Pass {
|
||||||
CleanupModule(mod, removed_ports);
|
CleanupModule(mod, removed_ports);
|
||||||
}
|
}
|
||||||
|
|
||||||
void CleanupModule(RTLIL::Module* module, std::map< RTLIL::IdString, std::set<RTLIL::IdString> >& removed_ports)
|
void CleanupModule(Module *module, dict<IdString, pool<IdString>> &removed_ports)
|
||||||
{
|
{
|
||||||
log("Removing now-unused cell ports in module %s\n", module->name.c_str());
|
log("Removing now-unused cell ports in module %s\n", module->name.c_str());
|
||||||
|
|
||||||
|
@ -80,11 +83,11 @@ struct RmportsPassPass : public Pass {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void ScanModule(RTLIL::Module* module, std::map< RTLIL::IdString, std::set<RTLIL::IdString> >& removed_ports)
|
void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports)
|
||||||
{
|
{
|
||||||
log("Finding unconnected ports in module %s\n", module->name.c_str());
|
log("Finding unconnected ports in module %s\n", module->name.c_str());
|
||||||
|
|
||||||
std::set<RTLIL::IdString> used_ports;
|
pool<IdString> used_ports;
|
||||||
|
|
||||||
// See what wires are used.
|
// See what wires are used.
|
||||||
// Start by checking connections between named wires
|
// Start by checking connections between named wires
|
||||||
|
@ -110,10 +113,10 @@ struct RmportsPassPass : public Pass {
|
||||||
//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());
|
//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());
|
||||||
|
|
||||||
if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
|
if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
|
||||||
used_ports.emplace(w1->name);
|
used_ports.insert(w1->name);
|
||||||
|
|
||||||
if( (w2->port_input || w2->port_output) && (used_ports.find(w2->name) == used_ports.end()) )
|
if( (w2->port_input || w2->port_output) && (used_ports.find(w2->name) == used_ports.end()) )
|
||||||
used_ports.emplace(w2->name);
|
used_ports.insert(w2->name);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -132,25 +135,25 @@ struct RmportsPassPass : public Pass {
|
||||||
|
|
||||||
// log(" sig %s\n", sig->name.c_str());
|
// log(" sig %s\n", sig->name.c_str());
|
||||||
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
|
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
|
||||||
used_ports.emplace(sig->name);
|
used_ports.insert(sig->name);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Now that we know what IS used, get rid of anything that isn't in that list
|
// Now that we know what IS used, get rid of anything that isn't in that list
|
||||||
std::set<RTLIL::IdString> unused_ports;
|
pool<IdString> unused_ports;
|
||||||
for(auto port : module->ports)
|
for(auto port : module->ports)
|
||||||
{
|
{
|
||||||
if(used_ports.find(port) != used_ports.end())
|
if(used_ports.find(port) != used_ports.end())
|
||||||
continue;
|
continue;
|
||||||
unused_ports.emplace(port);
|
unused_ports.insert(port);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Print the ports out as we go through them
|
// Print the ports out as we go through them
|
||||||
for(auto port : unused_ports)
|
for(auto port : unused_ports)
|
||||||
{
|
{
|
||||||
log(" removing unused port %s\n", port.c_str());
|
log(" removing unused port %s\n", port.c_str());
|
||||||
removed_ports[module->name].emplace(port);
|
removed_ports[module->name].insert(port);
|
||||||
|
|
||||||
// Remove from ports list
|
// Remove from ports list
|
||||||
for(size_t i=0; i<module->ports.size(); i++)
|
for(size_t i=0; i<module->ports.size(); i++)
|
||||||
|
|
Loading…
Reference in a new issue