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https://github.com/YosysHQ/yosys
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Fix broken ice40_dsp
This commit is contained in:
Eddie Hung
parent
38e73a3788
commit
888ae1d05e
2 changed files with 85 additions and 113 deletions
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@ -1,7 +1,7 @@
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pattern ice40_dsp
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state <SigBit> clock
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state <bool> clock_pol
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state <bool> clock_pol cd_signed
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state <std::set<SigBit>> sigAset sigBset
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state <SigSpec> sigA sigB sigCD sigH sigO sigOused
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state <Cell*> addAB muxAB
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@ -21,13 +21,22 @@ code sigAset sigBset
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endcode
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code sigH
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SigSpec O;
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if (mul->type == $mul)
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sigH = mul->getPort(\Y);
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O = mul->getPort(\Y);
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else if (mul->type == \SB_MAC16)
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sigH = mul->getPort(\O);
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O = mul->getPort(\O);
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else log_abort();
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if (GetSize(sigH) <= 10)
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if (GetSize(O) <= 10)
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reject;
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// Only care about those bits that are used
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int i;
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for (i = 0; i < GetSize(O); i++) {
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if (nusers(O[i]) <= 1)
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break;
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sigH.append(O[i]);
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}
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log_assert(nusers(O.extract_end(i)) <= 1);
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endcode
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match ffA
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@ -136,17 +145,16 @@ match addB
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optional
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endmatch
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code addAB sigCD sigO
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bool CD_SIGNED = false;
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code addAB sigCD sigO cd_signed
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if (addA) {
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addAB = addA;
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sigCD = port(addAB, \B);
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CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
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cd_signed = param(addAB, \B_SIGNED).as_bool();
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}
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if (addB) {
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else if (addB) {
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addAB = addB;
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sigCD = port(addAB, \A);
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CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
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cd_signed = param(addAB, \A_SIGNED).as_bool();
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}
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if (addAB) {
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if (mul->type == \SB_MAC16) {
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@ -167,7 +175,6 @@ code addAB sigCD sigO
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reject;
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sigO = port(addAB, \Y);
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sigCD.extend_u0(32, CD_SIGNED);
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}
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endcode
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@ -186,105 +193,63 @@ match muxB
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optional
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endmatch
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code muxAB
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code muxAB sigO
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if (muxA)
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muxAB = muxA;
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else if (muxB)
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muxAB = muxB;
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if (muxAB)
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sigO = port(muxAB, \Y);
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endcode
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// Extract the bits of P that actually have a consumer
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// (as opposed to being a dummy)
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code sigOused
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for (int i = 0; i < GetSize(sigO); i++)
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if (!sigO[i].wire || nusers(sigO[i]) == 1)
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sigOused.append(State::Sx);
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else
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sigOused.append(sigO[i]);
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endcode
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match ffO
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// Ensure that register is not already used
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if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
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if nusers(sigO) == 2
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select ffO->type.in($dff)
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filter GetSize(port(ffO, \D)) >= GetSize(sigO)
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slice offset GetSize(port(ffO, \D))
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filter offset+GetSize(sigO) <= GetSize(port(ffO, \D)) && port(ffO, \D).extract(offset, GetSize(sigO)) == sigO
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optional
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endmatch
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match ffO_lo
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if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
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if !ffO && GetSize(sigO) > 16
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// Ensure that register is not already used
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if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
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if nusers(sigO.extract(0, 16)) == 2
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select ffO_lo->type.in($dff)
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filter GetSize(port(ffO_lo, \D)) >= 16
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slice offset GetSize(port(ffO_lo, \D))
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filter offset+GetSize(sigO) <= GetSize(port(ffO_lo, \D)) && port(ffO_lo, \D).extract(offset, 16) == sigO.extract(0, 16)
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optional
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endmatch
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code
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if (ffO_lo) {
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SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
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O.remove_const();
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auto ffO_loSet = port(ffO_lo, \D).to_sigbit_set();
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auto Oset = O.to_sigbit_set();
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if (!std::includes(ffO_loSet.begin(), ffO_loSet.end(), Oset.begin(), Oset.end()))
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code clock clock_pol sigO sigCD cd_signed
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Cell* ff = nullptr;
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if (ffO)
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ff = ffO;
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else if (ffO_lo)
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ff = ffO_lo;
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if (ff) {
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for (auto b : port(ff, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ff, \CLK).as_bit();
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bool cp = param(ff, \CLK_POLARITY).as_bool();
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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reject;
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}
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endcode
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match ffO_hi
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if GetSize(sigOused) > 16
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if nusers(sigOused.extract_end(16)) == 2
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select ffO_hi->type.in($dff)
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optional
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endmatch
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clock = c;
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clock_pol = cp;
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code
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if (ffO_hi) {
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SigSpec O = sigOused.extract_end(16);
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O.remove_const();
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auto ffO_hiSet = port(ffO_hi, \D).to_sigbit_set();
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auto Oset = O.to_sigbit_set();
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if (!std::includes(ffO_hiSet.begin(), ffO_hiSet.end(), Oset.begin(), Oset.end()))
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reject;
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}
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endcode
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code clock clock_pol sigO sigCD
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if (ffO_lo || ffO_hi) {
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if (mul->type == \SB_MAC16) {
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// Ensure that register is not already used
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if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
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param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
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reject;
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// Ensure that OLOADTOP/OLOADBOT is unused or zero
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if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
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|| (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
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reject;
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}
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if (ffO_lo) {
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for (auto b : port(ffO_lo, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffO_lo, \CLK).as_bit();
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bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
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}
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if (ffO_hi) {
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for (auto b : port(ffO_hi, \Q))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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SigBit c = port(ffO_hi, \CLK).as_bit();
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bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
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if (clock != SigBit() && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
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}
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sigO.replace(port(ff, \D), port(ff, \Q));
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// Loading value into output register is not
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// supported unless using accumulator
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@ -296,8 +261,13 @@ code clock clock_pol sigO sigCD
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else if (muxB)
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sigCD = port(muxAB, \A);
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else log_abort();
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sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
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cd_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
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}
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}
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sigCD.extend_u0(32, cd_signed);
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endcode
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code
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accept;
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endcode
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