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ast, read_verilog: refactoring

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This commit is contained in:
Emil J. Tywoniak 2025-06-18 12:39:32 +02:00
parent 31002cf259
commit 88800a16ea
7 changed files with 16 additions and 21 deletions
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frontends/ast/genrtlil.cc
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@ -1339,8 +1339,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// be instantiated for this type of AST node.
IdString type_name;
current_filename = filename;
switch (type)
{
// simply ignore this nodes.