mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-26 02:25:35 +00:00
Added final checks to "synth" and "synth_xilinx"
This commit is contained in:
parent
40f021e136
commit
881dcd8af9
2 changed files with 24 additions and 7 deletions
|
@ -98,6 +98,10 @@ struct SynthXilinxPass : public Pass {
|
|||
log(" techmap -map +/xilinx/cells_map.v\n");
|
||||
log(" clean\n");
|
||||
log("\n");
|
||||
log(" check:\n");
|
||||
log(" hierarchy -check\n");
|
||||
log(" check -noinit\n");
|
||||
log("\n");
|
||||
log(" edif:\n");
|
||||
log(" write_edif synth.edif\n");
|
||||
log("\n");
|
||||
|
@ -195,6 +199,12 @@ struct SynthXilinxPass : public Pass {
|
|||
Pass::call(design, "clean");
|
||||
}
|
||||
|
||||
if (check_label(active, run_from, run_to, "check"))
|
||||
{
|
||||
Pass::call(design, "hierarchy -check");
|
||||
Pass::call(design, "check -noinit");
|
||||
}
|
||||
|
||||
if (check_label(active, run_from, run_to, "edif"))
|
||||
{
|
||||
if (!edif_file.empty())
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue