3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-19 01:32:20 +00:00

Merge upstream

This commit is contained in:
Akash Levy 2025-03-05 07:54:26 -08:00
parent 12137c7ac4
commit 881080a827
43 changed files with 510 additions and 94 deletions

View file

@ -0,0 +1,39 @@
pattern muldiv
state <SigSpec> t x y
state <bool> is_signed
match mul
select mul->type == $mul
select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y))
endmatch
code t x y is_signed
t = port(mul, \Y);
x = port(mul, \A);
y = port(mul, \B);
is_signed = param(mul, \A_SIGNED).as_bool();
branch;
std::swap(x, y);
endcode
match div
select div->type.in($div)
index <SigSpec> port(div, \A) === t
index <SigSpec> port(div, \B) === x
filter param(div, \A_SIGNED).as_bool() == is_signed
endmatch
code
SigSpec div_y = port(div, \Y);
SigSpec val_y = y;
if (GetSize(div_y) != GetSize(val_y))
val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
did_something = true;
log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
module->connect(div_y, val_y);
autoremove(div);
accept;
endcode