mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Removed forgotten debug code

Browse source
This commit is contained in:
Andrew Zonenberg 2016-04-01 23:39:32 -07:00
parent 2386885f22
commit 87e7cd9fbd
1 changed files with 1 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/greenpak4/greenpak4_counters.cc
View file

@ -347,8 +347,6 @@ void greenpak4_counters_worker(
log_id(extract.rwire->name),
count_reg_src.c_str());
log("blah");
//Wipe all of the old connections to the ALU
cell->unsetPort("\\A");
cell->unsetPort("\\B");
@ -363,8 +361,6 @@ void greenpak4_counters_worker(
cell->unsetParam("\\B_WIDTH");
cell->unsetParam("\\Y_WIDTH");
log("asdf");
//Change the cell type
cell->type = celltype;
@ -382,8 +378,6 @@ void greenpak4_counters_worker(
cell->setPort("\\RST", RTLIL::SigSpec(false));
}
log("world");
//Hook up other stuff
cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value));