mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity

Juggle opt calls in synth_xilinx

Browse source
This commit is contained in:
Eddie Hung 2019-04-11 09:13:39 -07:00
parent 227cc54c16
commit 87b8d29a90
2 changed files with 44 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/xilinx/synth_xilinx.cc
View file

@ -118,7 +118,7 @@ struct SynthXilinxPass : public Pass
log("\n");
log(" map_cells:\n");
log(" techmap -map +/xilinx/cells_map.v\n");
log(" clean\n");
log(" opt -fast\n");
log("\n");
log(" map_luts:\n");
log(" techmap -map +/techmap.v\n");
@ -258,11 +258,10 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "fine"))
{
Pass::call(design, "opt -fast -full");
Pass::call(design, "opt -fast");
Pass::call(design, "memory_map");
Pass::call(design, "dffsr2dff");
Pass::call(design, "dff2dffe");
Pass::call(design, "opt -full");
if (vpr) {
Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
@ -282,6 +281,7 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "opt -full");
Pass::call(design, "techmap -map +/techmap.v");
if (abc == "abc9")
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));