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Adding tests for dynamic part select optimisation

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diego 2020-04-16 13:31:05 -05:00
parent e86ba3b94d
commit 87910732f1
7 changed files with 161 additions and 0 deletions
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19
tests/arch/common/dynamic_part_select/forloop_select.v Normal file
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module forloop_select #(parameter WIDTH=256, SELW=4)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input en,
output reg [WIDTH-1:0] dout);
reg [SELW-1:0] sel;
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk)
begin
if (en) begin
for (sel = 0; sel < 4'hf; sel=sel+1'b1)
dout[(ctrl*sel)+:SLICE] <= din;
end
end
endmodule

19
tests/arch/common/dynamic_part_select/multiple_blocking.v Normal file
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module multiple_blocking #(parameter WIDTH=256, SELW=2)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input [SELW-1:0] sel ,
output reg [WIDTH:0] dout);
localparam SLICE = WIDTH/(SELW**2);
reg [9:0] a;
reg [SELW-1:0] b;
reg [15:0] c;
always @(posedge clk) begin
a = ctrl + 1;
b = sel - 1;
c = ~din;
dout = dout + 1;
dout[a*b+:SLICE] = c;
end
endmodule

14
tests/arch/common/dynamic_part_select/nonblocking.v Normal file
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module nonblocking #(parameter WIDTH=256, SELW=2)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input [SELW-1:0] sel ,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk) begin
dout <= dout + 1;
dout[ctrl*sel+:SLICE] <= din ;
end
endmodule

13
tests/arch/common/dynamic_part_select/original.v Normal file
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module original #(parameter WIDTH=256, SELW=2)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input [SELW-1:0] sel ,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk)
begin
dout[ctrl*sel+:SLICE] <= din ;
end
endmodule

24
tests/arch/common/dynamic_part_select/reset_test.v Normal file
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module reset_test #(parameter WIDTH=256, SELW=2)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input [SELW-1:0] sel ,
input wire reset,
output reg [WIDTH-1:0] dout);
reg [5:0] i;
wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}};
localparam SLICE = WIDTH/(SELW**2);
// Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for
// whatever reason.
always @(posedge clk) begin
if (reset) begin: reset_mask
for (i = 0; i < 16; i=i+1) begin
dout[i*rval+:SLICE] <= 32'hDEAD;
end
end
//else begin
dout[ctrl*sel+:SLICE] <= din;
//end
end
endmodule

13
tests/arch/common/dynamic_part_select/reversed.v Normal file
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module reversed #(parameter WIDTH=256, SELW=2)
(input clk ,
input [9:0] ctrl ,
input [15:0] din ,
input [SELW-1:0] sel ,
output reg [WIDTH-1:0] dout);
localparam SLICE = WIDTH/(SELW**2);
always @(posedge clk) begin
dout[(1024-ctrl*sel)-:SLICE] <= din;
end
endmodule