mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-13 17:36:16 +00:00
Code Activity

Add counter.sv SVA test

Browse source
This commit is contained in:
Clifford Wolf 2017-07-27 12:37:16 +02:00
parent 2336d5508b
commit 877ff1f75e
1 changed files with 29 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

29
tests/sva/counter.sv Normal file
View file

@ -0,0 +1,29 @@
module top (input clk, reset, up, down, output reg [7:0] cnt);
always @(posedge clk) begin
if (reset)
cnt <= 0;
else if (up)
cnt <= cnt + 1;
else if (down)
cnt <= cnt - 1;
end
default clocking @(posedge clk); endclocking
default disable iff (reset);
assert property (up |=> cnt == $past(cnt) + 8'd1);
// assert property (up [*2] |=> cnt == $past(cnt, 2) + 8'd2);
// assert property (up ##1 up |=> cnt == $past(cnt, 2) + 8'd2);
`ifndef FAIL
assume property (down |-> !up);
`endif
assert property (down |=> cnt == $past(cnt) - 8'd1);
property down_n(n);
down [*n] |=> cnt == $past(cnt, n) + n;
endproperty
// assert property (down_n(3));
// assert property (down_n(5));
endmodule