mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Added GP_DLATCH and GP_DLATCHI

Browse source
This commit is contained in:
Andrew Zonenberg 2016-12-05 23:49:06 -08:00
parent 981f014301
commit 8767cdcac9
1 changed files with 18 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

18
techlibs/greenpak4/cells_sim.v
View file

@ -240,6 +240,24 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
end end
endmodule endmodule
module GP_DLATCH(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= D;
end
endmodule
module GP_DLATCHI(input D, input nCLK, output reg Q);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if(!nCLK)
Q <= ~D;
end
endmodule
module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q); module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
parameter [0:0] INIT = 1'bx; parameter [0:0] INIT = 1'bx;
initial Q = INIT; initial Q = INIT;