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Merge 3d72dd198f into 25f2a88770

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489
kernel/ff.cc
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@ -21,245 +21,316 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initvals, cell_->name) // sorry
{ template<typename InputType, typename OutputType, typename = std::enable_if_t<std::is_base_of_v<FfTypeData, OutputType>>>
cell = cell_; void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
sig_q = cell->getPort(ID::Q); Cell* cell = nullptr;
width = GetSize(sig_q); IdString type;
attributes = cell->attributes; constexpr bool have_cell = std::is_same_v<InputType, Cell*>;
if constexpr (std::is_same_v<InputType, IdString>) {
type = flop;
} else {
static_assert(std::is_same_v<InputType, Cell*>);
cell = flop;
type = flop->type;
}
if constexpr (have_cell) {
info.sig_q = cell->getPort(ID::Q);
info.width = GetSize(info.sig_q);
info.attributes = cell->attributes;
if (initvals)
info.val_init = (*initvals)(info.sig_q);
}
if (initvals)
val_init = (*initvals)(sig_q);
std::string type_str = cell->type.str(); std::string type_str = type.str();
if (cell->type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) { if (type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
if (cell->type.in(ID($anyinit), ID($ff))) { if (type.in(ID($anyinit), ID($ff))) {
has_gclk = true; info.has_gclk = true;
sig_d = cell->getPort(ID::D); if constexpr (have_cell)
if (cell->type == ID($anyinit)) { info.sig_d = cell->getPort(ID::D);
is_anyinit = true; if (type == ID($anyinit)) {
log_assert(val_init.is_fully_undef()); info.is_anyinit = true;
if constexpr (have_cell)
log_assert(info.val_init.is_fully_undef());
} }
} else if (cell->type == ID($sr)) { } else if (type == ID($sr)) {
// No data input at all. // No data input at all.
} else if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) { } else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
has_aload = true; info.has_aload = true;
sig_aload = cell->getPort(ID::EN); if constexpr (have_cell) {
pol_aload = cell->getParam(ID::EN_POLARITY).as_bool(); info.sig_aload = cell->getPort(ID::EN);
sig_ad = cell->getPort(ID::D); info.pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
info.sig_ad = cell->getPort(ID::D);
}
} else { } else {
has_clk = true; info.has_clk = true;
sig_clk = cell->getPort(ID::CLK); if constexpr (have_cell) {
pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool(); info.sig_clk = cell->getPort(ID::CLK);
sig_d = cell->getPort(ID::D); info.pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
info.sig_d = cell->getPort(ID::D);
}
} }
if (cell->type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) { if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
has_ce = true; info.has_ce = true;
sig_ce = cell->getPort(ID::EN); if constexpr (have_cell) {
pol_ce = cell->getParam(ID::EN_POLARITY).as_bool(); info.sig_ce = cell->getPort(ID::EN);
info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
}
} }
if (cell->type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) { if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
has_sr = true; info.has_sr = true;
sig_clr = cell->getPort(ID::CLR); if constexpr (have_cell) {
sig_set = cell->getPort(ID::SET); info.sig_clr = cell->getPort(ID::CLR);
pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool(); info.sig_set = cell->getPort(ID::SET);
pol_set = cell->getParam(ID::SET_POLARITY).as_bool(); info.pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
}
} }
if (cell->type.in(ID($aldff), ID($aldffe))) { if (type.in(ID($aldff), ID($aldffe))) {
has_aload = true; info.has_aload = true;
sig_aload = cell->getPort(ID::ALOAD); if constexpr (have_cell) {
pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool(); info.sig_aload = cell->getPort(ID::ALOAD);
sig_ad = cell->getPort(ID::AD); info.pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
info.sig_ad = cell->getPort(ID::AD);
}
} }
if (cell->type.in(ID($adff), ID($adffe), ID($adlatch))) { if (type.in(ID($adff), ID($adffe), ID($adlatch))) {
has_arst = true; info.has_arst = true;
sig_arst = cell->getPort(ID::ARST); if constexpr (have_cell) {
pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool(); info.sig_arst = cell->getPort(ID::ARST);
val_arst = cell->getParam(ID::ARST_VALUE); info.pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
info.val_arst = cell->getParam(ID::ARST_VALUE);
}
} }
if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) { if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
has_srst = true; info.has_srst = true;
sig_srst = cell->getPort(ID::SRST); if constexpr (have_cell) {
pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool(); info.sig_srst = cell->getPort(ID::SRST);
val_srst = cell->getParam(ID::SRST_VALUE); info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
ce_over_srst = cell->type == ID($sdffce); info.val_srst = cell->getParam(ID::SRST_VALUE);
}
info.ce_over_srst = type == ID($sdffce);
} }
} else if (cell->type == ID($_FF_)) { } else if (type == ID($_FF_)) {
is_fine = true; info.is_fine = true;
has_gclk = true; info.has_gclk = true;
sig_d = cell->getPort(ID::D); if constexpr (have_cell)
info.sig_d = cell->getPort(ID::D);
} else if (type_str.substr(0, 5) == "$_SR_") { } else if (type_str.substr(0, 5) == "$_SR_") {
is_fine = true; info.is_fine = true;
has_sr = true; info.has_sr = true;
pol_set = type_str[5] == 'P'; info.pol_set = type_str[5] == 'P';
pol_clr = type_str[6] == 'P'; info.pol_clr = type_str[6] == 'P';
sig_set = cell->getPort(ID::S); if constexpr (have_cell) {
sig_clr = cell->getPort(ID::R); info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
}
} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) { } else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[6] == 'P';
pol_clk = type_str[6] == 'P'; if constexpr (have_cell) {
sig_clk = cell->getPort(ID::C); info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
}
} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) { } else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[7] == 'P';
pol_clk = type_str[7] == 'P'; info.has_ce = true;
sig_clk = cell->getPort(ID::C); info.pol_ce = type_str[8] == 'P';
has_ce = true; if constexpr (have_cell) {
pol_ce = type_str[8] == 'P'; info.sig_d = cell->getPort(ID::D);
sig_ce = cell->getPort(ID::E); info.sig_clk = cell->getPort(ID::C);
info.sig_ce = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) { } else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[6] == 'P';
pol_clk = type_str[6] == 'P'; info.has_arst = true;
sig_clk = cell->getPort(ID::C); info.pol_arst = type_str[7] == 'P';
has_arst = true; info.val_arst = type_str[8] == '1' ? State::S1 : State::S0;
pol_arst = type_str[7] == 'P'; if constexpr (have_cell) {
sig_arst = cell->getPort(ID::R); info.sig_d = cell->getPort(ID::D);
val_arst = type_str[8] == '1' ? State::S1 : State::S0; info.sig_clk = cell->getPort(ID::C);
info.sig_arst = cell->getPort(ID::R);
}
} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) { } else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[7] == 'P';
pol_clk = type_str[7] == 'P'; info.has_arst = true;
sig_clk = cell->getPort(ID::C); info.pol_arst = type_str[8] == 'P';
has_arst = true; info.val_arst = type_str[9] == '1' ? State::S1 : State::S0;
pol_arst = type_str[8] == 'P'; info.has_ce = true;
sig_arst = cell->getPort(ID::R); info.pol_ce = type_str[10] == 'P';
val_arst = type_str[9] == '1' ? State::S1 : State::S0; if constexpr (have_cell) {
has_ce = true; info.sig_d = cell->getPort(ID::D);
pol_ce = type_str[10] == 'P'; info.sig_clk = cell->getPort(ID::C);
sig_ce = cell->getPort(ID::E); info.sig_arst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) { } else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[8] == 'P';
pol_clk = type_str[8] == 'P'; info.has_aload = true;
sig_clk = cell->getPort(ID::C); info.pol_aload = type_str[9] == 'P';
has_aload = true; if constexpr (have_cell) {
pol_aload = type_str[9] == 'P'; info.sig_d = cell->getPort(ID::D);
sig_aload = cell->getPort(ID::L); info.sig_clk = cell->getPort(ID::C);
sig_ad = cell->getPort(ID::AD); info.sig_aload = cell->getPort(ID::L);
info.sig_ad = cell->getPort(ID::AD);
}
} else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) { } else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[9] == 'P';
pol_clk = type_str[9] == 'P'; info.has_aload = true;
sig_clk = cell->getPort(ID::C); info.pol_aload = type_str[10] == 'P';
has_aload = true; info.has_ce = true;
pol_aload = type_str[10] == 'P'; info.pol_ce = type_str[11] == 'P';
sig_aload = cell->getPort(ID::L); if constexpr (have_cell) {
sig_ad = cell->getPort(ID::AD); info.sig_d = cell->getPort(ID::D);
has_ce = true; info.sig_clk = cell->getPort(ID::C);
pol_ce = type_str[11] == 'P'; info.sig_aload = cell->getPort(ID::L);
sig_ce = cell->getPort(ID::E); info.sig_ad = cell->getPort(ID::AD);
info.sig_ce = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) { } else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[8] == 'P';
pol_clk = type_str[8] == 'P'; info.has_sr = true;
sig_clk = cell->getPort(ID::C); info.pol_set = type_str[9] == 'P';
has_sr = true; info.pol_clr = type_str[10] == 'P';
pol_set = type_str[9] == 'P'; if constexpr (have_cell) {
pol_clr = type_str[10] == 'P'; info.sig_d = cell->getPort(ID::D);
sig_set = cell->getPort(ID::S); info.sig_clk = cell->getPort(ID::C);
sig_clr = cell->getPort(ID::R); info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
}
} else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) { } else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[9] == 'P';
pol_clk = type_str[9] == 'P'; info.has_sr = true;
sig_clk = cell->getPort(ID::C); info.pol_set = type_str[10] == 'P';
has_sr = true; info.pol_clr = type_str[11] == 'P';
pol_set = type_str[10] == 'P'; info.has_ce = true;
pol_clr = type_str[11] == 'P'; info.pol_ce = type_str[12] == 'P';
sig_set = cell->getPort(ID::S); if constexpr (have_cell) {
sig_clr = cell->getPort(ID::R); info.sig_d = cell->getPort(ID::D);
has_ce = true; info.sig_clk = cell->getPort(ID::C);
pol_ce = type_str[12] == 'P'; info.sig_set = cell->getPort(ID::S);
sig_ce = cell->getPort(ID::E); info.sig_clr = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) { } else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[7] == 'P';
pol_clk = type_str[7] == 'P'; info.has_srst = true;
sig_clk = cell->getPort(ID::C); info.pol_srst = type_str[8] == 'P';
has_srst = true; info.val_srst = type_str[9] == '1' ? State::S1 : State::S0;
pol_srst = type_str[8] == 'P'; if constexpr (have_cell) {
sig_srst = cell->getPort(ID::R); info.sig_d = cell->getPort(ID::D);
val_srst = type_str[9] == '1' ? State::S1 : State::S0; info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
}
} else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) { } else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[8] == 'P';
pol_clk = type_str[8] == 'P'; info.has_srst = true;
sig_clk = cell->getPort(ID::C); info.pol_srst = type_str[9] == 'P';
has_srst = true; info.val_srst = type_str[10] == '1' ? State::S1 : State::S0;
pol_srst = type_str[9] == 'P'; info.has_ce = true;
sig_srst = cell->getPort(ID::R); info.pol_ce = type_str[11] == 'P';
val_srst = type_str[10] == '1' ? State::S1 : State::S0; if constexpr (have_cell) {
has_ce = true; info.sig_d = cell->getPort(ID::D);
pol_ce = type_str[11] == 'P'; info.sig_clk = cell->getPort(ID::C);
sig_ce = cell->getPort(ID::E); info.sig_srst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) { } else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
is_fine = true; info.is_fine = true;
sig_d = cell->getPort(ID::D); info.has_clk = true;
has_clk = true; info.pol_clk = type_str[9] == 'P';
pol_clk = type_str[9] == 'P'; info.has_srst = true;
sig_clk = cell->getPort(ID::C); info.pol_srst = type_str[10] == 'P';
has_srst = true; info.val_srst = type_str[11] == '1' ? State::S1 : State::S0;
pol_srst = type_str[10] == 'P'; info.has_ce = true;
sig_srst = cell->getPort(ID::R); info.pol_ce = type_str[12] == 'P';
val_srst = type_str[11] == '1' ? State::S1 : State::S0; info.ce_over_srst = true;
has_ce = true; if constexpr (have_cell) {
pol_ce = type_str[12] == 'P'; info.sig_d = cell->getPort(ID::D);
sig_ce = cell->getPort(ID::E); info.sig_clk = cell->getPort(ID::C);
ce_over_srst = true; info.sig_srst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) { } else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
is_fine = true; info.is_fine = true;
has_aload = true; info.has_aload = true;
sig_ad = cell->getPort(ID::D); info.has_aload = true;
has_aload = true; info.pol_aload = type_str[9] == 'P';
pol_aload = type_str[9] == 'P'; if constexpr (have_cell) {
sig_aload = cell->getPort(ID::E); info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
}
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) { } else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
is_fine = true; info.is_fine = true;
has_aload = true; info.has_aload = true;
sig_ad = cell->getPort(ID::D); info.has_aload = true;
has_aload = true; info.pol_aload = type_str[9] == 'P';
pol_aload = type_str[9] == 'P'; info.has_arst = true;
sig_aload = cell->getPort(ID::E); info.pol_arst = type_str[10] == 'P';
has_arst = true; info.val_arst = type_str[11] == '1' ? State::S1 : State::S0;
pol_arst = type_str[10] == 'P'; if constexpr (have_cell) {
sig_arst = cell->getPort(ID::R); info.sig_ad = cell->getPort(ID::D);
val_arst = type_str[11] == '1' ? State::S1 : State::S0; info.sig_aload = cell->getPort(ID::E);
info.sig_arst = cell->getPort(ID::R);
}
} else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) { } else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
is_fine = true; info.is_fine = true;
has_aload = true; info.has_aload = true;
sig_ad = cell->getPort(ID::D); info.has_aload = true;
has_aload = true; info.pol_aload = type_str[11] == 'P';
pol_aload = type_str[11] == 'P'; info.has_sr = true;
sig_aload = cell->getPort(ID::E); info.pol_set = type_str[12] == 'P';
has_sr = true; info.pol_clr = type_str[13] == 'P';
pol_set = type_str[12] == 'P'; if constexpr (have_cell) {
pol_clr = type_str[13] == 'P'; info.sig_ad = cell->getPort(ID::D);
sig_set = cell->getPort(ID::S); info.sig_aload = cell->getPort(ID::E);
sig_clr = cell->getPort(ID::R); info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
}
} else { } else {
log_assert(0); log_assert(0);
} }
if (has_aload && !has_clk && !has_sr && !has_arst && sig_ad.is_fully_const()) { if constexpr (have_cell)
// Plain D latches with const D treated specially. if (info.has_aload && !info.has_clk && !info.has_sr && !info.has_arst && info.sig_ad.is_fully_const()) {
has_aload = false; // Plain D latches with const D treated specially.
has_arst = true; info.has_aload = false;
sig_arst = sig_aload; info.has_arst = true;
pol_arst = pol_aload; info.sig_arst = info.sig_aload;
val_arst = sig_ad.as_const(); info.pol_arst = info.pol_aload;
} info.val_arst = info.sig_ad.as_const();
}
}
FfTypeData::FfTypeData(IdString type) : FfTypeData()
{
manufacture_info(type, *this, nullptr);
}
FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initvals, cell_->name)
{
cell = cell_;
manufacture_info(cell, *this, initvals);
} }
FfData FfData::slice(const std::vector<int> &bits) { FfData FfData::slice(const std::vector<int> &bits) {

78
kernel/ff.h
View file

@ -78,31 +78,20 @@ YOSYS_NAMESPACE_BEGIN
// - has_arst [does not correspond to a native cell, represented as dlatch with const D input] // - has_arst [does not correspond to a native cell, represented as dlatch with const D input]
// - empty set [not a cell — will be emitted as a simple direct connection] // - empty set [not a cell — will be emitted as a simple direct connection]
struct FfData { struct FfTypeData {
Module *module; FfTypeData(IdString type);
FfInitVals *initvals; FfTypeData() {
Cell *cell; has_clk = false;
IdString name; has_gclk = false;
// The FF output. has_ce = false;
SigSpec sig_q; has_aload = false;
// The sync data input, present if has_clk or has_gclk. has_srst = false;
SigSpec sig_d; has_arst = false;
// The async data input, present if has_aload. has_sr = false;
SigSpec sig_ad; ce_over_srst = false;
// The sync clock, present if has_clk. is_fine = false;
SigSpec sig_clk; is_anyinit = false;
// The clock enable, present if has_ce. }
SigSpec sig_ce;
// The async load enable, present if has_aload.
SigSpec sig_aload;
// The async reset, preset if has_arst.
SigSpec sig_arst;
// The sync reset, preset if has_srst.
SigSpec sig_srst;
// The async clear (per-lane), present if has_sr.
SigSpec sig_clr;
// The async set (per-lane), present if has_sr.
SigSpec sig_set;
// True if this is a clocked (edge-sensitive) flip-flop. // True if this is a clocked (edge-sensitive) flip-flop.
bool has_clk; bool has_clk;
// True if this is a $ff, exclusive with every other has_*. // True if this is a $ff, exclusive with every other has_*.
@ -143,9 +132,38 @@ struct FfData {
bool pol_clr; bool pol_clr;
bool pol_set; bool pol_set;
// The value loaded by sig_arst. // The value loaded by sig_arst.
// Zero length if unknowable from just type
Const val_arst; Const val_arst;
// The value loaded by sig_srst. // The value loaded by sig_srst.
// Zero length if unknowable from just type
Const val_srst; Const val_srst;
};
struct FfData : FfTypeData {
Module *module;
FfInitVals *initvals;
Cell *cell;
IdString name;
// The FF output.
SigSpec sig_q;
// The sync data input, present if has_clk or has_gclk.
SigSpec sig_d;
// The async data input, present if has_aload.
SigSpec sig_ad;
// The sync clock, present if has_clk.
SigSpec sig_clk;
// The clock enable, present if has_ce.
SigSpec sig_ce;
// The async load enable, present if has_aload.
SigSpec sig_aload;
// The async reset, preset if has_arst.
SigSpec sig_arst;
// The sync reset, preset if has_srst.
SigSpec sig_srst;
// The async clear (per-lane), present if has_sr.
SigSpec sig_clr;
// The async set (per-lane), present if has_sr.
SigSpec sig_set;
// The initial value at power-up. // The initial value at power-up.
Const val_init; Const val_init;
// The FF data width in bits. // The FF data width in bits.
@ -154,16 +172,6 @@ struct FfData {
FfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) { FfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {
width = 0; width = 0;
has_clk = false;
has_gclk = false;
has_ce = false;
has_aload = false;
has_srst = false;
has_arst = false;
has_sr = false;
ce_over_srst = false;
is_fine = false;
is_anyinit = false;
pol_clk = false; pol_clk = false;
pol_aload = false; pol_aload = false;
pol_ce = false; pol_ce = false;

1
kernel/rtlil.h
View file

@ -582,7 +582,6 @@ template <> struct IDMacroHelper<-1> {
namespace RTLIL { namespace RTLIL {
extern dict<std::string, std::string> constpad; extern dict<std::string, std::string> constpad;
[[deprecated("Call cell->is_builtin_ff() instead")]]
const pool<IdString> &builtin_ff_cell_types(); const pool<IdString> &builtin_ff_cell_types();
static inline std::string escape_id(const std::string &str) { static inline std::string escape_id(const std::string &str) {

1
passes/cmds/Makefile.inc
View file

@ -57,3 +57,4 @@ OBJS += passes/cmds/abstract.o
OBJS += passes/cmds/test_select.o OBJS += passes/cmds/test_select.o
OBJS += passes/cmds/timeest.o OBJS += passes/cmds/timeest.o
OBJS += passes/cmds/linecoverage.o OBJS += passes/cmds/linecoverage.o
OBJS += passes/cmds/icell_liberty.o

37
passes/cmds/box_derive.cc
View file

@ -51,6 +51,9 @@ struct BoxDerivePass : Pass {
log(" replaces the internal Yosys naming scheme in which the names of derived\n"); log(" replaces the internal Yosys naming scheme in which the names of derived\n");
log(" modules start with '$paramod$')\n"); log(" modules start with '$paramod$')\n");
log("\n"); log("\n");
log(" -apply_derived_type\n");
log(" use the derived modules\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *d) override void execute(std::vector<std::string> args, RTLIL::Design *d) override
{ {
@ -59,11 +62,14 @@ struct BoxDerivePass : Pass {
size_t argidx; size_t argidx;
IdString naming_attr; IdString naming_attr;
IdString base_name; IdString base_name;
bool apply_mode = false;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-naming_attr" && argidx + 1 < args.size()) if (args[argidx] == "-naming_attr" && argidx + 1 < args.size())
naming_attr = RTLIL::escape_id(args[++argidx]); naming_attr = RTLIL::escape_id(args[++argidx]);
else if (args[argidx] == "-base" && argidx + 1 < args.size()) else if (args[argidx] == "-base" && argidx + 1 < args.size())
base_name = RTLIL::escape_id(args[++argidx]); base_name = RTLIL::escape_id(args[++argidx]);
else if (args[argidx] == "-apply")
apply_mode = true;
else else
break; break;
} }
@ -90,24 +96,29 @@ struct BoxDerivePass : Pass {
auto index = std::make_pair(base->name, cell->parameters); auto index = std::make_pair(base->name, cell->parameters);
if (cell->parameters.empty() || done.count(index)) if (cell->parameters.empty())
continue; continue;
IdString derived_type = base->derive(d, cell->parameters); if (!done.count(index)) {
Module *derived = d->module(derived_type); IdString derived_type = base->derive(d, cell->parameters);
log_assert(derived && "Failed to derive module\n"); Module *derived = d->module(derived_type);
log_debug("derived %s\n", derived_type); log_assert(derived && "Failed to derive module\n");
log("derived %s\n", derived_type);
if (!naming_attr.empty() && derived->has_attribute(naming_attr)) { if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr)); IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
if (!new_name.isPublic()) if (!new_name.isPublic())
log_error("Derived module %s cannot be renamed to private name %s.\n", log_error("Derived module %s cannot be renamed to private name %s.\n",
log_id(derived), log_id(new_name)); log_id(derived), log_id(new_name));
derived->attributes.erase(naming_attr); derived->attributes.erase(naming_attr);
d->rename(derived, new_name); d->rename(derived, new_name);
}
done[index] = derived;
} }
done[index] = derived; if (apply_mode)
cell->type = done[index]->name;
} }
} }
} }

32
passes/cmds/chtype.cc
View file

@ -22,6 +22,27 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
static void publish(RTLIL::IdString& id) {
if (id.begins_with("$")) {
log_debug("publishing %s\n", id.c_str());
id = "\\" + id.str();
log_debug("published %s\n", id.c_str());
}
}
static void publish_design(RTLIL::Design* design) {
auto saved_modules = design->modules_;
design->modules_.clear();
for (auto& [name, mod] : saved_modules) {
publish(mod->name);
design->modules_[mod->name] = mod;
for (auto* cell : mod->cells()) {
publish(cell->type);
}
}
}
struct ChtypePass : public Pass { struct ChtypePass : public Pass {
ChtypePass() : Pass("chtype", "change type of cells in the design") { } ChtypePass() : Pass("chtype", "change type of cells in the design") { }
void help() override void help() override
@ -38,12 +59,16 @@ struct ChtypePass : public Pass {
log(" -map <old_type> <new_type>\n"); log(" -map <old_type> <new_type>\n");
log(" change cells types that match <old_type> to <new_type>\n"); log(" change cells types that match <old_type> to <new_type>\n");
log("\n"); log("\n");
log(" -publish_icells\n");
log(" change internal cells types to public types\n");
log("\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
IdString set_type; IdString set_type;
dict<IdString, IdString> map_types; dict<IdString, IdString> map_types;
bool publish_mode = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -58,10 +83,17 @@ struct ChtypePass : public Pass {
map_types[old_type] = new_type; map_types[old_type] = new_type;
continue; continue;
} }
if (args[argidx] == "-publish_icells") {
publish_mode = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (publish_mode)
publish_design(design);
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())

217
passes/cmds/icell_liberty.cc Normal file
View file

@ -0,0 +1,217 @@
#include "kernel/yosys.h"
#include "kernel/celltypes.h"
#include "kernel/ff.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct LibertyStubber {
CellTypes ct;
LibertyStubber() {
ct.setup();
ct.setup_internals_ff();
}
void liberty_prefix(std::ostream& f)
{
f << "/*\n";
f << stringf("\tModels interfaces of select Yosys internal cell.\n");
f << stringf("\tLikely contains INCORRECT POLARITIES.\n");
f << stringf("\tImpractical for any simulation, synthesis, or timing.\n");
f << stringf("\tIntended purely for SDC expansion.\n");
f << stringf("\tDo not microwave or tumble dry.\n");
f << stringf("\tGenerated by %s\n", yosys_maybe_version());
f << "*/\n";
f << "library (yosys) {\n";
f << "\tinput_threshold_pct_fall : 50;\n";
f << "\tinput_threshold_pct_rise : 50;\n";
f << "\toutput_threshold_pct_fall : 50;\n";
f << "\toutput_threshold_pct_rise : 50;\n";
f << "\tslew_lower_threshold_pct_fall : 1;\n";
f << "\tslew_lower_threshold_pct_rise : 1;\n";
f << "\tslew_upper_threshold_pct_fall : 99;\n";
f << "\tslew_upper_threshold_pct_rise : 99;\n";
}
void liberty_suffix(std::ostream& f)
{
f << "}\n";
}
struct LibertyItemizer {
std::ostream& f;
int indent;
LibertyItemizer(std::ostream& f) : f(f), indent(0) {};
void item(std::string key, std::string val)
{
f << std::string(indent, '\t') << key << " : \"" << val << "\";\n";
}
};
void liberty_flop(Module* base, Module* derived, std::ostream& f)
{
auto base_name = base->name.str().substr(1);
auto derived_name = derived->name.str().substr(1);
FfTypeData ffType(base_name);
LibertyItemizer i(f);
if (ffType.has_gclk) {
log_warning("Formal flip flop %s can't be modeled\n", base_name.c_str());
return;
}
if (ffType.has_ce) {
log_warning("DFFE %s can't be modeled\n", base_name.c_str());
return;
}
f << "\tcell (\"" << derived_name << "\") {\n";
auto& base_type = ct.cell_types[base_name];
i.indent = 3;
auto sorted_ports = derived->ports;
// Hack for CLK and C coming before Q does
auto cmp = [](IdString l, IdString r) { return l.str() < r.str(); };
std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
std::string clock_pin_name = "";
for (auto x : sorted_ports) {
std::string port_name = RTLIL::unescape_id(x);
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
if (is_input && !is_output) {
i.item("direction", "input");
} else if (!is_input && is_output) {
i.item("direction", "output");
} else {
i.item("direction", "inout");
}
if (port_name == "CLK" || port_name == "C") {
i.item("clock", "true");
clock_pin_name = port_name;
}
if (port_name == "Q") {
i.item("function", "IQ");
f << "\t\t\ttiming () {\n";
i.indent++;
log_assert(clock_pin_name.size());
i.item("related_pin", clock_pin_name);
i.indent--;
f << "\t\t\t}\n";
}
f << "\t\t}\n";
}
f << "\t\tff (\"IQ\",\"IQ_N\") {\n";
i.indent = 3;
// TODO polarities?
if (ffType.has_clk) {
auto pin = ffType.is_fine ? "C" : "CLK";
i.item("clocked_on", pin);
}
if (ffType.has_arst) {
auto meaning = (ffType.val_arst == State::S1) ? "preset" : "clear";
auto pin = ffType.is_fine ? "R" : "ARST";
i.item(meaning, pin);
}
auto next_state = ffType.has_ce ? "D & EN" : "D";
i.item("next_state", next_state);
f << "\t\t}\n";
// bool has_aload;
// bool has_srst;
// bool has_arst;
// bool has_sr;
f << "\t}\n";
}
void liberty_cell(Module* base, Module* derived, std::ostream& f)
{
auto base_name = base->name.str().substr(1);
auto derived_name = derived->name.str().substr(1);
if (!ct.cell_types.count(base_name)) {
log_debug("skip skeleton for %s\n", base_name.c_str());
return;
}
if (RTLIL::builtin_ff_cell_types().count(base_name))
return liberty_flop(base, derived, f);
auto& base_type = ct.cell_types[base_name];
f << "\tcell (\"" << derived_name << "\") {\n";
for (auto x : derived->ports) {
bool is_input = base_type.inputs.count(x);
bool is_output = base_type.outputs.count(x);
f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
if (is_input && !is_output) {
f << "\t\t\tdirection : input;\n";
} else if (!is_input && is_output) {
f << "\t\t\tdirection : output;\n";
} else {
f << "\t\t\tdirection : inout;\n";
}
f << "\t\t}\n";
}
f << "\t}\n";
}
};
struct IcellLiberty : Pass {
IcellLiberty() : Pass("icell_liberty", "write Liberty interfaces for used internal cells") {}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" icell_liberty <liberty_file>\n"); // TODO
log("\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *d) override
{
log_header(d, "Executing ICELL_LIBERTY pass.\n");
size_t argidx;
IdString naming_attr;
std::string liberty_filename;
std::ofstream* liberty_file = new std::ofstream;
for (argidx = 1; argidx < args.size(); argidx++) {
break;
}
if (argidx < args.size())
liberty_filename = args[argidx++];
else
log_error("no Liberty filename specified\n");
// extra_args(args, argidx, d);
if (liberty_filename.size()) {
liberty_file->open(liberty_filename.c_str());
if (liberty_file->fail()) {
delete liberty_file;
log_error("Can't open file `%s' for writing: %s\n", liberty_filename.c_str(), strerror(errno));
}
}
pool<RTLIL::IdString> done;
LibertyStubber stubber = {};
if (liberty_file)
stubber.liberty_prefix(*liberty_file);
for (auto module : d->selected_modules()) {
for (auto cell : module->selected_cells()) {
Module *inst_module = d->module(cell->type);
if (!inst_module || !inst_module->get_blackbox_attribute())
continue;
Module *base = inst_module;
if (!done.count(base->name)) {
stubber.liberty_cell(base, base, *liberty_file);
done.insert(base->name);
}
}
}
if (liberty_file) {
stubber.liberty_suffix(*liberty_file);
delete liberty_file;
}
}
} IcellLiberty;
PRIVATE_NAMESPACE_END

2
techlibs/common/Makefile.inc
View file

@ -2,6 +2,8 @@
ifneq ($(SMALL),1) ifneq ($(SMALL),1)
OBJS += techlibs/common/synth.o OBJS += techlibs/common/synth.o
OBJS += techlibs/common/prep.o OBJS += techlibs/common/prep.o
OBJS += techlibs/common/opensta.o
OBJS += techlibs/common/sdc_expand.o
endif endif
GENFILES += techlibs/common/simlib_help.inc GENFILES += techlibs/common/simlib_help.inc

125
techlibs/common/opensta.cc Normal file
View file

@ -0,0 +1,125 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
#if !defined(YOSYS_DISABLE_SPAWN)
struct OpenstaPass : public Pass
{
const char* default_sta_cmd = "sta";
OpenstaPass() : Pass("opensta", "run OpenSTA") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opensta [options]\n");
log("\n");
// TOOD
log("\n");
log(" -exe <command>\n");
log(" use <command> to run OpenSTA instead of \"%s\"\n", default_sta_cmd);
log("\n");
log(" -sdc-in <filename>\n");
log(" expand SDC input file <filename>\n");
log("\n");
log(" -sdc-out <filename>\n");
log(" expand SDC file to output file <filename>\n");
log("\n");
log(" -nocleanup\n");
log("\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
string opensta_exe = "sta";
string sdc_filename, sdc_expanded_filename;
string tempdir_name, script_filename;
string verilog_filename, liberty_filename;
bool cleanup = true;
log_header(design, "Executing OPENSTA pass.\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-exe" && argidx+1 < args.size()) {
opensta_exe = args[++argidx];
continue;
}
if (args[argidx] == "-sdc-in" && argidx+1 < args.size()) {
sdc_filename = args[++argidx];
continue;
}
if (args[argidx] == "-sdc-out" && argidx+1 < args.size()) {
sdc_expanded_filename = args[++argidx];
continue;
}
if (args[argidx] == "-verilog" && argidx+1 < args.size()) {
verilog_filename = args[++argidx];
continue;
}
if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
liberty_filename = args[++argidx];
continue;
}
if (args[argidx] == "-nocleanup") {
cleanup = false;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (cleanup)
tempdir_name = get_base_tmpdir() + "/";
else
tempdir_name = "_tmp_";
tempdir_name += proc_program_prefix() + "yosys-opensta-XXXXXX";
tempdir_name = make_temp_dir(tempdir_name);
script_filename = tempdir_name + "/opensta.tcl";
// script_filename
auto top_mod = design->top_module();
if (!top_mod)
log_error("Can't find top module in current design!\n");
std::ofstream f_script;
f_script.open(script_filename);
f_script << "read_verilog " << verilog_filename << "\n";
f_script << "read_lib " << liberty_filename << "\n";
f_script << "link_design " << RTLIL::unescape_id(top_mod->name) << "\n";
f_script << "read_sdc " << sdc_filename << "\n";
f_script << "write_sdc " << sdc_expanded_filename << "\n";
f_script.close();
std::string command = opensta_exe + " -exit " + script_filename;
auto process_line = [](const std::string &line) {
if (line.find("Creating black box") != std::string::npos)
return;
if (line.find("does not match net size") != std::string::npos)
return;
log("OpenSTA: %s", line.c_str());
};
int ret = run_command(command, process_line);
if (ret)
log_error("OpenSTA return %d (error)\n", ret);
else
log("sdc_expanded_filename: %s\n", sdc_expanded_filename.c_str());
if (cleanup) {
log("Removing temp directory.\n");
remove_directory(tempdir_name);
}
log_pop();
}
} OpenstaPass;
#endif
PRIVATE_NAMESPACE_END

150
techlibs/common/sdc_expand.cc Normal file
View file

@ -0,0 +1,150 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SdcexpandPass : public ScriptPass
{
const char* default_sta_cmd = "sta";
SdcexpandPass() : ScriptPass("sdc_expand", "run OpenSTA") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" sdc_expand [options]\n");
log("\n");
// TODO
log("\n");
log(" -exe <command>\n");
log(" use <command> to run OpenSTA instead of \"%s\"\n", default_sta_cmd);
log("\n");
log(" -sdc-in <filename>\n");
log(" expand SDC file <filename>\n");
log("\n");
log(" -nocleanup\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string opensta_exe, sdc_filename, sdc_expanded_filename;
bool cleanup = true;
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing SDC_EXPAND pass.\n");
string run_from, run_to;
opensta_exe = "sta";
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-exe" && argidx+1 < args.size()) {
opensta_exe = args[++argidx];
continue;
}
if (args[argidx] == "-sdc-in" && argidx+1 < args.size()) {
sdc_filename = args[++argidx];
continue;
}
if (args[argidx] == "-sdc-out" && argidx+1 < args.size()) {
sdc_expanded_filename = args[++argidx];
continue;
}
if (args[argidx] == "-nocleanup") {
cleanup = false;
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos) {
run_from = args[++argidx];
run_to = args[argidx];
} else {
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
}
continue;
}
break;
}
if (sdc_filename.empty())
log_cmd_error("Missing -sdc-in argument\n");
if (sdc_expanded_filename.empty())
log_cmd_error("Missing -sdc-out argument\n");
extra_args(args, argidx, design);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
log_header(design, "Executing OPENSTA pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
std::string tempdir_name;
run("design -save pre_expand");
run("proc");
run("memory");
// run("dfflegalize -cell $dff");
if (help_mode) {
tempdir_name = "<tmp_dir>";
} else {
if (cleanup)
tempdir_name = get_base_tmpdir() + "/";
else
tempdir_name = "_tmp_";
tempdir_name += proc_program_prefix() + "yosys-sdc_expand-XXXXXX";
tempdir_name = make_temp_dir(tempdir_name);
}
std::string verilog_path = tempdir_name + "/elaborated.v";
std::string write_verilog_cmd = "write_verilog -norename -noexpr -attr2comment -defparam ";
run(write_verilog_cmd + verilog_path);
run("read_verilog -setattr whitebox -defer -DSIMLIB_NOCHECKS +/simlib.v");
run("proc");
run("hierarchy -auto-top");
run("chtype -publish_icells");
std::string liberty_path = tempdir_name + "/yosys.lib";
run("icell_liberty " + liberty_path);
std::string opensta_pass_call = "opensta -exe ";
opensta_pass_call += help_mode ? "<exe>" : opensta_exe;
opensta_pass_call += " -sdc-in ";
opensta_pass_call += help_mode ? "<sdc-in>" : sdc_filename;
opensta_pass_call += " -sdc-out ";
opensta_pass_call += help_mode ? "<sdc-out>" : sdc_expanded_filename;
opensta_pass_call += " -verilog ";
opensta_pass_call += help_mode ? "<verilog>" : verilog_path;
opensta_pass_call += " -liberty ";
opensta_pass_call += help_mode ? "<tmp_dir>/yosys.lib" : liberty_path;
if (!cleanup)
opensta_pass_call += " -nocleanup";
run(opensta_pass_call);
if (!help_mode) {
if (cleanup) {
log("Removing temp directory.\n");
remove_directory(tempdir_name);
} else {
log("Keeping temp directory %s\n", tempdir_name.c_str());
}
}
run("design -load pre_expand");
}
} SdcexpandPass;
PRIVATE_NAMESPACE_END

40
tests/various/box_derive.ys
View file

@ -34,6 +34,7 @@ module top;
endmodule endmodule
EOF EOF
design -save before
box_derive -naming_attr final_name top box_derive -naming_attr final_name top
select -assert-mod-count 1 =aa1 select -assert-mod-count 1 =aa1
@ -48,6 +49,45 @@ select -assert-mod-count 1 =cc1
select -assert-mod-count 0 =cc2 select -assert-mod-count 0 =cc2
select -assert-mod-count 0 =cc3 select -assert-mod-count 0 =cc3
# no instances of the new derived modules
# you could use wildcards like t:aa* here - if that wasn't just broken
select -assert-count 0 t:aa1 t:aa2 t:aa3
select -assert-count 0 t:bb1 t:bb2 t:bb3
select -assert-count 0 t:cc1 t:cc2 t:cc3
design -load before
# same command but with -apply_derived_type
box_derive -apply_derived_type -naming_attr final_name top
# same derived modules created as without -apply_derived_type
select -assert-mod-count 1 =aa1
select -assert-mod-count 1 =aa2
select -assert-mod-count 0 =aa3
select -assert-mod-count 1 =bb1
select -assert-mod-count 0 =bb2
select -assert-mod-count 1 =bb3
select -assert-mod-count 1 =cc1
select -assert-mod-count 0 =cc2
select -assert-mod-count 0 =cc3
# but we have instances of the new derived modules
select -assert-count 1 t:aa1
select -assert-count 1 t:aa2
select -assert-count 0 t:aa3
select -assert-count 1 t:bb1
select -assert-count 0 t:bb2
select -assert-count 1 t:bb3
select -assert-count 2 t:cc1
select -assert-count 0 t:cc2
select -assert-count 0 t:cc3
# we are expecting the original aa, bb, cc modules # we are expecting the original aa, bb, cc modules
# and 5 specializations generated by box_derive # and 5 specializations generated by box_derive
select -assert-mod-count 8 =A:whitebox select -assert-mod-count 8 =A:whitebox