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bufnorm: Refactor and fix incremental bufNormalize
This fixes some edge cases the previous version didn't handle properly by simplifying the logic of determining directly driven wires and representatives to use as buffer inputs.
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cbc1055517
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86fb2f16f7
3 changed files with 270 additions and 115 deletions
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@ -2829,6 +2829,13 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
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delete_wire_worker.wires_p = &wires;
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rewrite_sigspecs2(delete_wire_worker);
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if (design->flagBufferedNormalized) {
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for (auto wire : wires) {
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buf_norm_wire_queue.erase(wire);
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buf_norm_connect_index.erase(wire);
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}
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}
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for (auto &it : wires) {
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log_assert(wires_.count(it->name) != 0);
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wires_.erase(it->name);
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