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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-03-08 15:11:04 -08:00 • committed by GitHub
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5 changed files with 190 additions and 16 deletions
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2
passes/opt/share.cc
View file

@ -87,7 +87,7 @@ struct ShareWorker
queue_bits.clear();
for (auto &pbit : portbits) {
if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) {
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) {
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());

8
techlibs/intel/common/brams_map_m9k.v
View file

@ -63,10 +63,10 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.width_byteena_a (1), // Forced value
.numwords_b ( NUMWORDS ),
.numwords_a ( NUMWORDS ),
.widthad_b ( CFG_DBITS ),
.width_b ( CFG_ABITS ),
.widthad_a ( CFG_DBITS ),
.width_a ( CFG_ABITS )
.widthad_b ( CFG_ABITS ),
.width_b ( CFG_DBITS ),
.widthad_a ( CFG_ABITS ),
.width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ (
.data_a(B1DATA),
.address_a(B1ADDR),

55
techlibs/intel/max10/cells_sim.v
View file

@ -2,6 +2,7 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2024 Richard Herveille <richard.herveille@roalogic.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -289,4 +290,56 @@ module fiftyfivenm_pll
output vcooverrange;
output vcounderrange;
endmodule // cycloneive_pll
endmodule // max10_pll
/* MAX10 MULT clearbox model */
(* blackbox *)
module fiftyfivenm_mac_mult (
dataa,
datab,
dataout,
signa,
signb,
aclr,
clk,
ena
);
parameter dataa_clock = "none";
parameter dataa_width = 18;
parameter datab_clock = "none";
parameter datab_width = 18;
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_type = "fiftyfivenm_mac_mult";
input [dataa_width -1:0] dataa;
input [datab_width -1:0] datab;
output [(dataa_width+datab_width)-1:0] dataout;
input signa;
input signb;
input aclr;
input clk;
input ena;
endmodule //fiftyfivenm_mac_mult
module fiftyfivenm_mac_out (
dataa,
dataout,
aclr,
clk,
ena
);
parameter dataa_width = 38;
parameter output_clock = "none";
parameter lpm_type = "fiftyfivenm_mac_out";
input [dataa_width-1:0] dataa;
output [dataa_width-1:0] dataout;
input aclr;
input clk;
input ena;
endmodule //fiftyfivenm_mac_out

73
techlibs/intel/max10/dsp_map.v Normal file
View file

@ -0,0 +1,73 @@
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [A_WIDTH+B_WIDTH-1:0] mult_result;
fiftyfivenm_mac_mult #(
.dataa_clock ("none"),
.datab_clock ("none"),
.signa_clock ("none"),
.signb_clock ("none"),
.dataa_width (A_WIDTH),
.datab_width (B_WIDTH),
.lpm_type ("fiftyfivenm_mac_mult")
) _TECHMAP_REPLACE_mac_mult (
//Data path
.dataa ( A ),
.datab ( B ),
.dataout( mult_result ),
.signa ( A_SIGNED != 0 ? 1'b1 : 1'b0),
.signb ( B_SIGNED != 0 ? 1'b1 : 1'b0)
);
fiftyfivenm_mac_out #(
.dataa_width (A_WIDTH + B_WIDTH),
.output_clock ("none"),
.lpm_type ("fiftyfivenm_mac_out")
) _TECHMAP_REPLACE_mac_out (
.dataa (mult_result),
.dataout (Y)
);
endmodule
module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [A_WIDTH+B_WIDTH-1:0] mult_result;
fiftyfivenm_mac_mult #(
.dataa_clock ("none"),
.datab_clock ("none"),
.signa_clock ("none"),
.signb_clock ("none"),
.dataa_width (A_WIDTH),
.datab_width (B_WIDTH),
.lpm_type ("fiftyfivenm_mac_mult")
) _TECHMAP_REPLACE_mac_mult (
//Data path
.dataa ( A ),
.datab ( B ),
.dataout( mult_result ),
.signa ( A_SIGNED != 0 ? 1'b1 : 1'b0),
.signb ( B_SIGNED != 0 ? 1'b1 : 1'b0)
);
fiftyfivenm_mac_out #(
.dataa_width (A_WIDTH + B_WIDTH),
.output_clock ("none"),
.lpm_type ("fiftyfivenm_mac_out")
) _TECHMAP_REPLACE_mac_out (
.dataa (mult_result),
.dataout (Y)
);
endmodule

68
techlibs/intel/synth_intel.cc
View file

@ -2,6 +2,7 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* Copyright (C) 2024 Richard Herveille <richard.herveille@roalogic.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -62,12 +63,19 @@ struct SynthIntelPass : public ScriptPass {
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -dff\n");
log(" pass DFFs to ABC to perform sequential logic optimisations\n");
log(" (EXPERIMENTAL)\n");
log("\n");
log(" -iopads\n");
log(" use IO pad cells in output netlist\n");
log("\n");
log(" -nobram\n");
log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -nodsp\n");
log(" do not map multipliers to MUL18/MUL9 cells\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
@ -80,7 +88,7 @@ struct SynthIntelPass : public ScriptPass {
}
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram, iopads;
bool retime, flatten, nobram, dff, nodsp, iopads;
void clear_flags() override
{
@ -91,6 +99,8 @@ struct SynthIntelPass : public ScriptPass {
retime = false;
flatten = true;
nobram = false;
dff = false;
nodsp = false;
iopads = false;
}
@ -130,6 +140,14 @@ struct SynthIntelPass : public ScriptPass {
iopads = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-nodsp") {
nodsp = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
@ -178,15 +196,42 @@ struct SynthIntelPass : public ScriptPass {
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (flatten && check_label("flatten", "(unless -noflatten)")) {
run("proc");
run("flatten");
run("tribuf -logic");
run("deminout");
}
if (check_label("coarse")) {
run("synth -run coarse");
run("proc");
if (flatten || help_mode)
run("flatten", "(skip if -noflatten)");
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
if (help_mode) {
run("techmap -map +mul2dsp.v [...]", "(unless -nodsp)");
} else if (!nodsp) {
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL18X18");
run("chtype -set $mul t:$__soft_mul");
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__MUL18X18");
run("chtype -set $mul t:$__soft_mul");
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL9X9");
run("chtype -set $mul t:$__soft_mul");
run("alumacc");
run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt.c_str()));
} else {
run("alumacc");
}
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
@ -219,7 +264,10 @@ struct SynthIntelPass : public ScriptPass {
}
if (check_label("map_luts")) {
run("abc -lut 4" + string(retime ? " -dff" : ""));
run("abc9 -lut 4 -W 300" + string(dff ? " -dff" : ""));
run("clean");
run("opt -fast");
run("autoname");
run("clean");
}