mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

Adjust buf-normalized mode

Browse source
This commit is contained in:
Martin Povišer 2024-05-21 13:08:40 +02:00
parent 80119386c0
commit 865df26fac
5 changed files with 49 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

14
kernel/rtlil.h
View file

@ -1510,6 +1510,10 @@ public:
#endif
};
namespace RTLIL_BACKEND {
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
}
struct RTLIL::Wire : public RTLIL::AttrObject
{
unsigned int hashidx_;
@ -1521,6 +1525,12 @@ protected:
Wire();
~Wire();
friend struct RTLIL::Design;
friend struct RTLIL::Cell;
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
RTLIL::Cell *driverCell_ = nullptr;
RTLIL::IdString driverPort_;
public:
// do not simply copy wires
Wire(RTLIL::Wire &other) = delete;
@ -1531,8 +1541,8 @@ public:
int width, start_offset, port_id;
bool port_input, port_output, upto, is_signed;
RTLIL::Cell *driverCell = nullptr;
RTLIL::IdString driverPort;
RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);