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https://github.com/YosysHQ/yosys
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Adjust buf-normalized mode
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parent
80119386c0
commit
865df26fac
5 changed files with 49 additions and 37 deletions
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@ -3575,10 +3575,12 @@ void RTLIL::Design::bufNormalize(bool enable)
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for (auto module : modules()) {
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module->bufNormQueue.clear();
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for (auto wire : module->wires()) {
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wire->driverCell = nullptr;
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wire->driverPort = IdString();
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wire->driverCell_ = nullptr;
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wire->driverPort_ = IdString();
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}
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}
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flagBufferedNormalized = false;
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return;
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}
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@ -3592,9 +3594,9 @@ void RTLIL::Design::bufNormalize(bool enable)
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continue;
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if (conn.second.is_wire()) {
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Wire *wire = conn.second.as_wire();
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log_assert(wire->driverCell == nullptr);
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wire->driverCell = cell;
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wire->driverPort = conn.first;
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log_assert(wire->driverCell_ == nullptr);
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wire->driverCell_ = cell;
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wire->driverPort_ = conn.first;
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} else {
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pair<RTLIL::Cell*, RTLIL::IdString> key(cell, conn.first);
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module->bufNormQueue.insert(key);
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@ -3614,7 +3616,7 @@ void RTLIL::Module::bufNormalize()
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if (!design->flagBufferedNormalized)
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return;
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while (GetSize(bufNormQueue))
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while (GetSize(bufNormQueue) || !connections_.empty())
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{
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pool<pair<RTLIL::Cell*, RTLIL::IdString>> queue;
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bufNormQueue.swap(queue);
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@ -3636,9 +3638,13 @@ void RTLIL::Module::bufNormalize()
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if (sig.is_wire()) {
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Wire *wire = sig.as_wire();
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log_assert(wire->driverCell == nullptr);
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wire->driverCell = cell;
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wire->driverPort = portname;
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if (wire->driverCell_) {
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log_error("Conflict between %s %s in module %s\n",
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log_id(cell), log_id(wire->driverCell_), log_id(this));
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}
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log_assert(wire->driverCell_ == nullptr);
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wire->driverCell_ = cell;
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wire->driverPort_ = portname;
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continue;
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}
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@ -3688,9 +3694,9 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
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if (conn_it->second.is_wire()) {
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Wire *w = conn_it->second.as_wire();
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if (w->driverCell == this && w->driverPort == portname) {
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w->driverCell = nullptr;
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w->driverPort = IdString();
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if (w->driverCell_ == this && w->driverPort_ == portname) {
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w->driverCell_ = nullptr;
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w->driverPort_ = IdString();
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}
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}
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@ -3705,12 +3711,12 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
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}
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Wire *w = signal.as_wire();
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if (w->driverCell != nullptr) {
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pair<RTLIL::Cell*, RTLIL::IdString> other_key(w->driverCell, w->driverPort);
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if (w->driverCell_ != nullptr) {
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pair<RTLIL::Cell*, RTLIL::IdString> other_key(w->driverCell_, w->driverPort_);
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module->bufNormQueue.insert(other_key);
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}
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w->driverCell = this;
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w->driverPort = portname;
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w->driverCell_ = this;
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w->driverPort_ = portname;
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module->bufNormQueue.erase(key);
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break;
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