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Adjust buf-normalized mode

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This commit is contained in:
Martin Povišer 2024-05-21 13:08:40 +02:00
parent 80119386c0
commit 865df26fac
5 changed files with 49 additions and 37 deletions
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2
kernel/celledges.cc
View file

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));

38
kernel/rtlil.cc
View file

@ -3575,10 +3575,12 @@ void RTLIL::Design::bufNormalize(bool enable)
for (auto module : modules()) {
module->bufNormQueue.clear();
for (auto wire : module->wires()) {
wire->driverCell = nullptr;
wire->driverPort = IdString();
wire->driverCell_ = nullptr;
wire->driverPort_ = IdString();
}
}
flagBufferedNormalized = false;
return;
}
@ -3592,9 +3594,9 @@ void RTLIL::Design::bufNormalize(bool enable)
continue;
if (conn.second.is_wire()) {
Wire *wire = conn.second.as_wire();
log_assert(wire->driverCell == nullptr);
wire->driverCell = cell;
wire->driverPort = conn.first;
log_assert(wire->driverCell_ == nullptr);
wire->driverCell_ = cell;
wire->driverPort_ = conn.first;
} else {
pair<RTLIL::Cell*, RTLIL::IdString> key(cell, conn.first);
module->bufNormQueue.insert(key);
@ -3614,7 +3616,7 @@ void RTLIL::Module::bufNormalize()
if (!design->flagBufferedNormalized)
return;
while (GetSize(bufNormQueue))
while (GetSize(bufNormQueue) || !connections_.empty())
{
pool<pair<RTLIL::Cell*, RTLIL::IdString>> queue;
bufNormQueue.swap(queue);
@ -3636,9 +3638,13 @@ void RTLIL::Module::bufNormalize()
if (sig.is_wire()) {
Wire *wire = sig.as_wire();
log_assert(wire->driverCell == nullptr);
wire->driverCell = cell;
wire->driverPort = portname;
if (wire->driverCell_) {
log_error("Conflict between %s %s in module %s\n",
log_id(cell), log_id(wire->driverCell_), log_id(this));
}
log_assert(wire->driverCell_ == nullptr);
wire->driverCell_ = cell;
wire->driverPort_ = portname;
continue;
}
@ -3688,9 +3694,9 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
if (conn_it->second.is_wire()) {
Wire *w = conn_it->second.as_wire();
if (w->driverCell == this && w->driverPort == portname) {
w->driverCell = nullptr;
w->driverPort = IdString();
if (w->driverCell_ == this && w->driverPort_ == portname) {
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
}
}
@ -3705,12 +3711,12 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
}
Wire *w = signal.as_wire();
if (w->driverCell != nullptr) {
pair<RTLIL::Cell*, RTLIL::IdString> other_key(w->driverCell, w->driverPort);
if (w->driverCell_ != nullptr) {
pair<RTLIL::Cell*, RTLIL::IdString> other_key(w->driverCell_, w->driverPort_);
module->bufNormQueue.insert(other_key);
}
w->driverCell = this;
w->driverPort = portname;
w->driverCell_ = this;
w->driverPort_ = portname;
module->bufNormQueue.erase(key);
break;

14
kernel/rtlil.h
View file

@ -1510,6 +1510,10 @@ public:
#endif
};
namespace RTLIL_BACKEND {
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
}
struct RTLIL::Wire : public RTLIL::AttrObject
{
unsigned int hashidx_;
@ -1521,6 +1525,12 @@ protected:
Wire();
~Wire();
friend struct RTLIL::Design;
friend struct RTLIL::Cell;
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
RTLIL::Cell *driverCell_ = nullptr;
RTLIL::IdString driverPort_;
public:
// do not simply copy wires
Wire(RTLIL::Wire &other) = delete;
@ -1531,8 +1541,8 @@ public:
int width, start_offset, port_id;
bool port_input, port_output, upto, is_signed;
RTLIL::Cell *driverCell = nullptr;
RTLIL::IdString driverPort;
RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);